/*****************************************************************************
 * @file     NANO1xx.h
 * @author   NuMicro MCU Software Team
 * @version  V1.07
 * @date     11. August 2011
 * @brief    CMSIS ARM Cortex-M0 Core Peripheral Access Layer Header File.
 *           This file contains all the peripheral register's definitions, 
 *           bits definitions and memory mapping for NuMicro Nano series.
 *
 * @note
 * Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved.
 *
 * @par
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 *
 ******************************************************************************/


#ifndef __NANO1xx_H__
#define __NANO1xx_H__

#ifdef __cplusplus
extern "C" {
#endif

/*
 * @brief NANO1xx Interrupt Number Definition 
 */

typedef enum IRQn
{
/******  Cortex-M0 Processor Exceptions Numbers *****************************************/
  NonMaskableInt_IRQn	= -14,    /*!< 2 Non Maskable Interrupt                         */
  HardFault_IRQn		= -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                 */
  SVCall_IRQn			= -5,     /*!< 11 Cortex-M0 SV Call Interrupt                   */
  PendSV_IRQn			= -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                   */
  SysTick_IRQn			= -1,     /*!< 15 Cortex-M0 System Tick Interrupt               */

/******  NANO1xx specific Interrupt Numbers ******************************************************/	
  BOD_IRQn              = 0,      /*!< Brownout low voltage detected interrupt                   */
  WDT_IRQn              = 1,      /*!< Watch Dog Timer interrupt                                 */
  EINT0_IRQn            = 2,      /*!< External signal interrupt from PB.14 pin                  */
  EINT1_IRQn            = 3,      /*!< External signal interrupt from PB.15 pin                  */
  GPABC_IRQn            = 4,      /*!< External signal interrupt from PA[15:0]/PB[13:0]/PC[15:0] */
  GPDEF_IRQn            = 5,      /*!< External interrupt from PD[15:0]/PE[15:0]/PF[15:0]        */
  PWM0_IRQn             = 6,      /*!< PWM 0 interrupt                                           */
  PWM1_IRQn             = 7,      /*!< PWM 1 interrupt                                           */
  TMR0_IRQn             = 8,      /*!< Timer 0 interrupt                                         */
  TMR1_IRQn             = 9,      /*!< Timer 1 interrupt                                         */
  TMR2_IRQn             = 10,     /*!< Timer 2 interrupt                                         */
  TMR3_IRQn             = 11,     /*!< Timer 3 interrupt                                         */
  UART0_IRQn            = 12,     /*!< UART0 interrupt                                           */
  UART1_IRQn            = 13,     /*!< UART1 interrupt                                           */
  SPI0_IRQn             = 14,     /*!< SPI0 interrupt                                            */
  SPI1_IRQn             = 15,     /*!< SPI1 interrupt                                            */
  SPI2_IRQn             = 16,     /*!< SPI2 interrupt                                            */
  HIRC_IRQn             = 17,     /*!< HIRC interrupt                                            */
  I2C0_IRQn             = 18,     /*!< I2C0 interrupt                                            */
  I2C1_IRQn             = 19,     /*!< I2C1 interrupt                                            */
  SC0_IRQn              = 21,     /*!< Smart Card 0 interrupt                                    */  
  SC1_IRQn              = 22,     /*!< Smart Card 1 interrupt                                    */  
  USBD_IRQn             = 23,     /*!< USB FS Device interrupt                                   */
  TK_IRQn               = 24,     /*!< Touch key interrupt                                       */
  LCD_IRQn              = 25,     /*!< LCD interrupt                                             */
  PDMA_IRQn             = 26,     /*!< PDMA interrupt                                            */
  I2S_IRQn              = 27,     /*!< I2S interrupt                                             */
  PDWU_IRQn             = 28,     /*!< Power Down Wake up interrupt                              */
  ADC_IRQn              = 29,     /*!< ADC interrupt                                             */
  DAC_IRQn              = 30,     /*!< DAC interrupt                                             */
  RTC_IRQn              = 31      /*!< Real time clock interrupt                                 */
  
} IRQn_Type;


/*
 * @brief Processor and Core Peripheral Section  
 */

/* Configuration of the Cortex-M0 Processor and Core Peripherals */
#define __MPU_PRESENT             0         /*!< MPU present or not                               */
#define __NVIC_PRIO_BITS          2         /*!< Number of Bits used for Priority Levels          */
#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */


#include "core_cm0.h"                       /* Cortex-M0 processor and core peripherals           */
#include "system_NANO1xx.h"                   /* System Header                                      */
#include "SysInfra.h"    
#include <stdint.h>

#if defined ( __CC_ARM   )
#pragma anon_unions
#endif

/* @addtogroup NANO1xx Specific Peripheral registers structures
 * @{
 */   

/*
 * @brief WatchDog Timer
 */
typedef struct
{
  union {
  __IO uint32_t  CTL;
                 struct {
                 __IO uint32_t  WTR:1;
	             __IO uint32_t  WTRE:1;
				 __IO uint32_t  WTWKE:1;
				 __IO uint32_t  WTE:1;
	             __IO uint32_t  WTIS:3;
                 __I  uint32_t  RESERVED0:25;
                 } CTL_BITS;
  };
  union {
  __IO uint32_t  IER;
  				struct {
                 __IO uint32_t  WDT_IE:1;
                 __I  uint32_t  RESERVED0:31;
                 } IER_BITS;
  };
  union {
  __IO uint32_t  ISR;
                 struct {
                 __IO uint32_t  WDT_IS:1;
                 __IO uint32_t  WDT_RST_IS:1;
                 __IO uint32_t  WDT_WAKE_IS:1;
                      uint32_t  RESERVED0:29;
                 } ISR_BITS;
  };
} WDT_TypeDef;


/* 
 * @brief Real Time Clock
 */
typedef struct
{
  __IO uint32_t  INIR;
  union {
  __IO uint32_t  AER;
                 struct {
                 __IO uint32_t  AER:16;
                 __I  uint32_t  ENF:1;
                      uint32_t  RESERVED0:15;
                 } AER_BITS;
  };
  union {
  __IO uint32_t  FCR;
                 struct {
                 __IO uint32_t  FRACTION:6;
                      uint32_t  RESERVED0:2;
                 __IO uint32_t  INTEGER:4;
                      uint32_t  RESERVED1:20;
                 } FCR_BITS;
  };
  union {
  __IO uint32_t  TLR;
                 struct {
                 __IO uint32_t  SEC:4;
                 __IO uint32_t  TEN_SEC:3;
                      uint32_t  RESERVED0:1;
                 __IO uint32_t  MIN:4;
                 __IO uint32_t  TEN_MIN:3;
                      uint32_t  RESERVED1:1;
                 __IO uint32_t  HR:4;
                 __IO uint32_t  TEN_HR:2;
                      uint32_t  RESERVED2:10;
                 } TLR_BITS;
  };
  union {
  __IO uint32_t  CLR;
                 struct {
                 __IO uint32_t  DAY:4;
                 __IO uint32_t  TEN_DAY:2;
                      uint32_t  RESERVED0:2;
                 __IO uint32_t  MON:4;
                 __IO uint32_t  TEN_MON:1;
                      uint32_t  RESERVED1:3;	   
                 __IO uint32_t  YEAR:4;
                 __IO uint32_t  TEN_YEAR:4;
                      uint32_t  RESERVED2:8;
                 } CLR_BITS;
  };
  union {
  __IO uint32_t  TSSR;
                 struct {
                 __IO uint32_t  HR24:1;
                      uint32_t  RESERVED0:31;
                 } TSSR_BITS;
  };
  union {
  __IO uint32_t  DWR;
                 struct {
                 __IO uint32_t  DWR:3;
                      uint32_t  RESERVED0:29;
                 } DWR_BITS;
  };
  union {
  __IO uint32_t  TAR;
                 struct {
                 __IO uint32_t  SEC:4;
                 __IO uint32_t  TEN_SEC:3;
                      uint32_t  RESERVED0:1;
                 __IO uint32_t  MIN:4;
                 __IO uint32_t  TEN_MIN:3;
                      uint32_t  RESERVED1:1;
                 __IO uint32_t  HR:4;
                 __IO uint32_t  TEN_HR:2;
                      uint32_t  RESERVED2:10;
                 } TAR_BITS;
  };
  union {
  __IO uint32_t  CAR;
                 struct {
                 __IO uint32_t  DAY:4;
                 __IO uint32_t  TEN_DAY:2;
                      uint32_t  RESERVED0:2;
                 __IO uint32_t  MON:4;
                 __IO uint32_t  TEN_MON:1;
                      uint32_t  RESERVED1:3;	   
                 __IO uint32_t  YEAR:4;
                 __IO uint32_t  TEN_YEAR:4;
                      uint32_t  RESERVED2:8;
                 } CAR_BITS;
  };
  union {
  __I  uint32_t  LIR;
                 struct {
                 __IO uint32_t  LIR:1;
                      uint32_t  RESERVED0:31;
                 } LIR_BITS;
  };
  union {
  __IO uint32_t  RIER;
                 struct {
                 __IO uint32_t  AIER:1;
                 __IO uint32_t  TIER:1;
                 __IO uint32_t  SNOOPIER:1;
                      uint32_t  RESERVED0:29;
                 } RIER_BITS;
  };
  union {
  __IO uint32_t  RIIR;
                 struct {
                 __IO uint32_t  AIS:1;
                 __IO uint32_t  TIS:1;
                 __IO uint32_t  SNOOPIS:1;
                      uint32_t  RESERVED0:29;
                 } RIIR_BITS;
  };
  union {
  __IO uint32_t  TTR;
                 struct {
                 __IO uint32_t  TTR:3;
                 __IO uint32_t  TWKE:1;
                      uint32_t  RESERVED0:28;
                 } TTR_BITS;
  };
       uint32_t  RESERVED0[2];
  union {
  __IO uint32_t  SPRCTL;
                 struct {
                 __IO uint32_t  SNOOPEN:1;
                 __IO uint32_t  SNOOPEDGE:1;
                      uint32_t  RESERVED0:5;
                 __I  uint32_t  SPRRDY:1;
                      uint32_t  RESERVED1:24;
                 } SPRCTL_BITS;
  };
  __IO uint32_t  SPR0;
  __IO uint32_t  SPR1;
  __IO uint32_t  SPR2;
  __IO uint32_t  SPR3;
  __IO uint32_t  SPR4;
  __IO uint32_t  SPR5;
  __IO uint32_t  SPR6;
  __IO uint32_t  SPR7;
  __IO uint32_t  SPR8;
  __IO uint32_t  SPR9;
  __IO uint32_t  SPR10;
  __IO uint32_t  SPR11;
  __IO uint32_t  SPR12;
  __IO uint32_t  SPR13;
  __IO uint32_t  SPR14;
  __IO uint32_t  SPR15;
  __IO uint32_t  SPR16;
  __IO uint32_t  SPR17;
  __IO uint32_t  SPR18;
  __IO uint32_t  SPR19;
} RTC_TypeDef;


/*
 * @brief General Timer
 */
typedef struct
{
  union {
  __IO uint32_t  CTL;
                 struct {
                 __IO uint32_t  TMR_EN:1;
                 __IO uint32_t  SW_RST:1;
                 __IO uint32_t  WAKE_EN:1;
				 __IO uint32_t  DBGACK_EN:1;
				 __IO uint32_t  MODE_SEL:2;
				      uint32_t  RESERVED0:1;
				 __I  uint32_t  TMR_ACT:1;
				 __IO uint32_t  ADC_TEEN:1;
				 __IO uint32_t  DAC_TEEN:1;
				 __IO uint32_t  PDMA_TEEN:1;
				 __IO uint32_t  CAP_TRG_EN:1;
				 __IO uint32_t  EVENT_EN:1;
				 __IO uint32_t  EVENT_EDGE:1;
				 __IO uint32_t  EVNT_DEB_EN:1;
				      uint32_t  RESERVED1:1;
				 __IO uint32_t  TCAP_EN:1;
                 __IO uint32_t  TCAP_MODE:1;
				 __IO uint32_t  TCAP_EDGE:2;				 
                 __IO uint32_t  CAP_CNT_MOD:1;
				      uint32_t  RESERVED2:1;
                 __IO uint32_t  TCAP_DEB_EN:1;
				      uint32_t  RESERVED3:1;
                 __IO uint32_t  INTR_TRG_EN:1;
                      uint32_t  RESERVED4:7;
                } CTL_BITS;
  };
  __IO uint32_t  PRECNT;
  __IO uint32_t  CMPR;
  union {
  __IO uint32_t  IER;
  				struct {
                 __IO uint32_t  TMR_IE:1;
				 __IO uint32_t  TCAP_IE:1;
                      uint32_t  RESERVED0:30;
                 } IER_BITS;
  };
  union {
  __IO uint32_t  ISR;
                 struct {
                 __IO uint32_t  TMR_IS:1;
				 __IO uint32_t  TCAP_IS:1;
                      uint32_t  RESERVED0:2;
				 __IO uint32_t  TMR_WAKE_STS:1;
                 __I  uint32_t  NCAP_DET_STS:1;
				      uint32_t  RESERVED1:26;
                 } ISR_BITS;
  };
  __I  uint32_t  DR;
  __I  uint32_t  TCAP;
} TIMER_TypeDef;


/*
 * @brief GPIO shadow registers
 */
typedef struct
{
   __I uint32_t  GPA_SHADOW;
   __I uint32_t  GPB_SHADOW;
   __I uint32_t  GPC_SHADOW;
   __I uint32_t  GPD_SHADOW;
   __I uint32_t  GPE_SHADOW;
   __I uint32_t  GPF_SHADOW;
} SHADOW_TypeDef;


/* 
 * @brief I2C
 */
typedef struct
{
  union {
  __IO uint32_t  CON;
                 struct {
                 __IO uint32_t  IPEN:1;
                 __IO uint32_t  ACK:1;
                 __IO uint32_t  STOP:1;
                 __IO uint32_t  START:1;
                 __O  uint32_t  TRIG:1;
                      uint32_t  RESERVED0:2;
                 __IO uint32_t  INTEN:1;
                      uint32_t  RESERVED1:24;
                 } CON_BITS;
  };
  union {
  __IO uint32_t  INTSTS;
                 struct {
                 __IO uint32_t  STAINTSTS:1;
                 __IO uint32_t  TOUTSTS:1;
                      uint32_t  RESERVED1:30;
                 } INTSTS_BITS;
  
  };
  __I  uint32_t  STATUS;
  __IO uint32_t  DIV;
  union {
  __IO uint32_t  TOUT;
                 struct {
                 __IO uint32_t  TOUTEN:1;
                 __IO uint32_t  DIV4:1;
                      uint32_t  RESERVED0:30;
                 } TOUT_BITS;
  };
  __IO uint32_t  DATA;
  union {
  __IO uint32_t  SADDR0;
                 struct {
                 __IO uint32_t  GCALL:1;
                 __IO uint32_t  SADDR:7;
                      uint32_t  RESERVED0:24;
                 } SADDR0_BITS;
  };
  union {
  __IO uint32_t  SADDR1;
                 struct {
                 __IO uint32_t  GCALL:1;
                 __IO uint32_t  SADDR:7;
                      uint32_t  RESERVED0:24;
                 } SADDR1_BITS;
  };
       uint32_t  RESERVED0;
       uint32_t  RESERVED1;
  union {
  __IO uint32_t  SAMASK0;
  				struct {
                      uint32_t  RESERVED0:1;
                 __IO uint32_t  SAMASK:7;
                      uint32_t  RESERVED1:24;
                 } SAMASK0_BITS;
  };               
  union {
  __IO uint32_t  SAMASK1;
  				struct {
                      uint32_t  RESERVED0:1;
                 __IO uint32_t  SAMASK:7;
                      uint32_t  RESERVED1:24;
                 } SAMASK1_BITS;
  };
} I2C_TypeDef;


/* 
 * @brief Serial Peripheral Interface (SPI)
 */
typedef struct
{
  union {
  __IO uint32_t  CTL;
                 struct {
                 __IO uint32_t  GO_BUSY:1;
                 __IO uint32_t  RX_NEG:1;
                 __IO uint32_t  TX_NEG:1;
                 __IO uint32_t  TX_BIT_LEN:5;
                 __IO uint32_t  TX_NUM:2;
                 __IO uint32_t  LSB:1;
                 __IO uint32_t  CLKP:1;
                 __IO uint32_t  SP_CYCLE:4;
                      uint32_t  RESERVED0:1;
                 __IO uint32_t  INTEN:1;
                 __IO uint32_t  SLAVE:1;
                 __IO uint32_t  REORDER:2;
                 __IO uint32_t  FIFOM:1;
                 __IO uint32_t  TWOB:1;
                 __IO uint32_t  VARCLK_EN:1;
                 __IO uint32_t  SCLK_DLY:3;
                      uint32_t  RESERVED1:4;
                 __IO uint32_t  WKEUP_EN:1;
                 } CTL_BITS;
  };
  union {
  __IO uint32_t  STATUS;
                 struct {
                 __IO uint32_t  RX_EMPTY:1;
                 __IO uint32_t  RX_FULL:1;
                 __IO uint32_t  TX_EMPTY:1;
                 __IO uint32_t  TX_FULL:1;
                 __I  uint32_t  LTRIG_FLAG:1;
                 	  uint32_t  RESERVED0:1;
                 __IO uint32_t  SLV_START_INTSTS:1;                           
                 __IO uint32_t  INTSTS:1;
                      uint32_t  RESERVED1:24;
                 } STATUS_BITS;
  }; 
  union {
  __IO uint32_t  CLKDIV;
                 struct {
                 __IO uint32_t  DIVIDER1:16;
                 __IO uint32_t  DIVIDER2:16;
                 } CLKDIV_BITS;
  };
  
  union {
  __IO uint32_t  SSR;
                 struct {
                 __IO uint32_t  SSR:2;
                 __IO uint32_t  SS_LVL:1;
                 __IO uint32_t  AUTOSS:1;
                 __IO uint32_t  SS_LTRIG:1;
                 __IO uint32_t  NOSLVSEL:1;
                      uint32_t  RESERVED0:2;
                 __IO uint32_t  SLV_ABORT:1;
                 __IO uint32_t  SSTA_INTEN:1;
                 	  uint32_t  RESERVED1:22;
                 } SSR_BITS;
  };
  __I  uint32_t  RX0;
  __I  uint32_t  RX1;
       uint32_t  RESERVED0;
       uint32_t  RESERVED1;
  __O  uint32_t  TX0;
  __O  uint32_t  TX1;
       uint32_t  RESERVED2;
       uint32_t  RESERVED3;
       uint32_t  RESERVED4;
  __IO uint32_t  VARCLK;
  union {
  __IO uint32_t  PDMA;
                 struct {
                 __IO uint32_t  TX_DMA_EN:1;
                 __IO uint32_t  RX_DMA_EN:1;
                 __I  uint32_t  PDMA_RST:1;
                      uint32_t  RESERVED0:29;
                 } PDMA_BITS;
  };
  union {
  __IO uint32_t  FFCLR;
                 struct {
                 __IO uint32_t  RX_CLR:1;
                 __IO uint32_t  TX_CLR:1;
                      uint32_t  RESERVED0:30;
                 } FFCLR_BITS;
  };
} SPI_TypeDef;


/*  
 * @brief PWM Generator and Capture Timer
 */
typedef struct
{
  union {
  __IO uint32_t  PRES;
                 struct {
                 __IO uint32_t  CP01:8;
                 __IO uint32_t  CP23:8;
                 __IO uint32_t  DZ01:8;
                 __IO uint32_t  DZ23:8;
                 } PRES_BITS;
  };
  union {
  __IO uint32_t  CLKSEL;
                 struct {
                 __IO uint32_t  CLKSEL0:3;
                      uint32_t  RESERVED0:1;
                 __IO uint32_t  CLKSEL1:3;
                      uint32_t  RESERVED1:1;
                 __IO uint32_t  CLKSEL2:3;
                      uint32_t  RESERVED2:1;
                 __IO uint32_t  CLKSEL3:3;
                      uint32_t  RESERVED3:1;
                 } CLKSEL_BITS;
  };
  union {
  __IO uint32_t  CTL;
                 struct {
                 __IO uint32_t  CH0EN:1;
                      uint32_t  RESERVED0:1;
                 __IO uint32_t  CH0INV:1;
                 __IO uint32_t  CH0MOD:1;
                 __IO uint32_t  DZEN01:1;
                 __IO uint32_t  DZEN23:1;
                      uint32_t  RESERVED1:2;
                 __IO uint32_t  CH1EN:1;
                      uint32_t  RESERVED2:1;
                 __IO uint32_t  CH1INV:1;
                 __IO uint32_t  CH1MOD:1;
                      uint32_t  RESERVED3:4;
                 __IO uint32_t  CH2EN:1;
                      uint32_t  RESERVED4:1;
                 __IO uint32_t  CH2INV:1;
                 __IO uint32_t  CH2MOD:1;
                      uint32_t  RESERVED5:4;
                 __IO uint32_t  CH3EN:1;
                      uint32_t  RESERVED6:1;
                 __IO uint32_t  CH3INV:1;
                 __IO uint32_t  CH3MOD:1;
                      uint32_t  RESERVED7:4;   
                 } CTL_BITS;
  };
  union {
  __IO uint32_t  INTEN;
                 struct {
                 __IO uint32_t  TMIE0:1;
                 __IO uint32_t  TMIE1:1;
                 __IO uint32_t  TMIE2:1;
                 __IO uint32_t  TMIE3:1;
	                  uint32_t  RESERVED0:28;
                 } INTEN_BITS;
  };
  union {
  __IO uint32_t  INTSTS;
                 struct {
                 __IO uint32_t  TMINT0:1;
                 __IO uint32_t  TMINT1:1;
                 __IO uint32_t  TMINT2:1;
                 __IO uint32_t  TMINT3:1;
				 __IO uint32_t 	Duty0SyncFlag:1;
				 __IO uint32_t 	Duty1SyncFlag:1;
				 __IO uint32_t 	Duty2SyncFlag:1;
				 __IO uint32_t 	Duty3SyncFlag:1;
				 __IO uint32_t  PresSyncFlag:1;
	                  uint32_t  RESERVED0:23;
                 } INTSTS_BITS;
  };
  union {
  __IO uint32_t  OE;
                 struct {
                 __IO uint32_t  CH0:1;
                 __IO uint32_t  CH1:1;
                 __IO uint32_t  CH2:1;
                 __IO uint32_t  CH3:1;
	                  uint32_t  RESERVED0:28;
	             } OE_BITS;
  };
       uint32_t  RESERVED0;
  union {
  __IO uint32_t  DUTY0;
                 struct {
                 __IO uint32_t  CN:16;
                 __IO uint32_t  CM:16;
                 } DUTY0_BITS;
  };
       uint32_t  RESERVED1[2];
   union {
  __IO uint32_t  DUTY1;
                 struct {
                 __IO uint32_t  CN:16;
                 __IO uint32_t  CM:16;
                 } DUTY1_BITS;
  };
       uint32_t  RESERVED2[2];
   union {
  __IO uint32_t  DUTY2;
                 struct {
                 __IO uint32_t  CN:16;
                 __IO uint32_t  CM:16;
                 } DUTY2_BITS;
  };
       uint32_t  RESERVED3[2];
    union {
  __IO uint32_t  DUTY3;
                 struct {
                 __IO uint32_t  CN:16;
                 __IO uint32_t  CM:16;
                 } DUTY3_BITS;
  };
       uint32_t  RESERVED4[2];
       uint32_t  RESERVED5;
       uint32_t  RESERVED6;
  union {     
  __IO uint32_t  CAPCTL;
                 struct {
                 __IO uint32_t  INV0:1;
                 __IO uint32_t  CAPCH0EN:1;
                 __IO uint32_t  CAPCH0PADEN:1;
                 __IO uint32_t  CH0PDMAEN:1;
                 __IO uint32_t  PDMACAPMOD0:2;
                 __IO uint32_t  CAPRELOADREN0:1;
                 __IO uint32_t  CAPRELOADFEN0:1;
                 __IO uint32_t  INV1:1;
                 __IO uint32_t  CAPCH1EN:1;
                 __IO uint32_t  CAPCH1PADEN:1;
                      uint32_t  RESERVED0:1;
                 __IO uint32_t  CH0RFORDER:1;
                 __IO uint32_t  CH01CASK:1;
                 __IO uint32_t  CAPRELOADREN1:1;
                 __IO uint32_t  CAPRELOADFEN1:1;
                 __IO uint32_t  INV2:1;
                 __IO uint32_t  CAPCH2EN:1;
                 __IO uint32_t  CAPCH2PADEN:1;
                 __IO uint32_t  CH2PDMAEN:1;
                 __IO uint32_t  PDMACAPMOD2:2;
                 __IO uint32_t  CAPRELOADREN2:1;
                 __IO uint32_t  CAPRELOADFEN2:1;
                 __IO uint32_t  INV3:1;
                 __IO uint32_t  CAPCH3EN:1;
                 __IO uint32_t  CAPCH3PADEN:1;
                      uint32_t  RESERVED1:1;
                 __IO uint32_t  CH3RFORDER:1;
                 __IO uint32_t  CH23CASK:1;
                 __IO uint32_t  CAPRELOADREN3:1;
                 __IO uint32_t  CAPRELOADFEN3:1;
                 } CAPCTL_BITS;
  };
  union {
  __IO uint32_t  CAPINTEN;
                 struct {
                 __IO uint32_t  CRL_IE0:1;
                 __IO uint32_t  CFL_IE0:1;
                      uint32_t  RESERVED0:6;
                 __IO uint32_t  CRL_IE1:1;
                 __IO uint32_t  CFL_IE1:1;
                      uint32_t  RESERVED1:6;
                 __IO uint32_t  CRL_IE2:1;
                 __IO uint32_t  CFL_IE2:1;
                      uint32_t  RESERVED2:6;
                 __IO uint32_t  CRL_IE3:1;
                 __IO uint32_t  CFL_IE3:1;
                      uint32_t  RESERVED3:6;
                 } CAPINTEN_BITS;
  };
  union {
  __IO uint32_t  CAPINTSTS;
                 struct {
                 __IO uint32_t  CAPIF0:1;
                 __IO uint32_t  CRLI0:1;
                 __IO uint32_t  CFLI0:1;
                 __IO uint32_t  CAPOVR0:1;
                 __IO uint32_t  CAPOVF0:1;
                      uint32_t  RESERVED0:3;
                 __IO uint32_t  CAPIF1:1;
                 __IO uint32_t  CRLI1:1;
                 __IO uint32_t  CFLI1:1;
                 __IO uint32_t  CAPOVR1:1;
                 __IO uint32_t  CAPOVF1:1;
                      uint32_t  RESERVED1:3;
                 __IO uint32_t  CAPIF2:1;
                 __IO uint32_t  CRLI2:1;
                 __IO uint32_t  CFLI2:1;
                 __IO uint32_t  CAPOVR2:1;
                 __IO uint32_t  CAPOVF2:1;
                      uint32_t  RESERVED2:3;
                 __IO uint32_t  CAPIF3:1;
                 __IO uint32_t  CRLI3:1;
                 __IO uint32_t  CFLI3:1;
                 __IO uint32_t  CAPOVR3:1;
                 __IO uint32_t  CAPOVF3:1;
                      uint32_t  RESERVED3:3;
                 } CAPINTSTS_BITS;
  };
  __I  uint32_t  CRL0;
  __I  uint32_t  CFL0;
  __I  uint32_t  CRL1;
  __I  uint32_t  CFL1;
  __I  uint32_t  CRL2;
  __I  uint32_t  CFL2;
  __I  uint32_t  CRL3;
  __I  uint32_t  CFL3;
  __I  uint32_t  CH0PDMA;
  __I  uint32_t  CH2PDMA;
} PWM_TypeDef;


/*  
 * @brief UART
 */
typedef struct
{
  union {
  __I  uint32_t  RBR;
  __O  uint32_t  THR;
  };
  union {
  __IO uint32_t  CTL;
                 struct {
                 __IO uint32_t  RX_RST:1;
                 __IO uint32_t  TX_RST:1;
                 __IO uint32_t  RX_DIS:1;
                 __IO uint32_t  TX_DIS:1;
                 __IO uint32_t  AUTO_RTS_EN:1;	  
                 __IO uint32_t  AUTO_CTS_EN:1;
                 __IO uint32_t  DMA_RX_EN:1;
                 __IO uint32_t  DMA_TX_EN:1;
	             __IO uint32_t  WAKE_CTS_EN:1;
                      uint32_t  RESERVED0:3;
                 __IO uint32_t  ABAUD_EN:1;
                 __I  uint32_t  RESERVE0:19;    
                 } CTL_BITS;
  };
  union {
  __IO uint32_t  TLCTL;
                 struct {
                 __IO uint32_t  DATA_LEN:2;
                 __IO uint32_t  NSB:1;
                 __IO uint32_t  PBE:1;
                 __IO uint32_t  EPE:1;
                 __IO uint32_t  SPE:1;	  
                 __IO uint32_t  BCB:1;
                 __I  uint32_t  RESERVED0:1;
	             __IO uint32_t  RFITL:2;
                 __I  uint32_t  RESERVED1:2;
                 __IO uint32_t  RTS_TRI_LEV:2; 
                 __I  uint32_t  RESERVED2:18;    
                 } TLCTL_BITS;
  };
  union {
  __IO uint32_t  IER;
                 struct {
                 __IO uint32_t  RDA_IE:1;
                 __IO uint32_t  THRE_IE:1;
                 __IO uint32_t  RLS_IE:1;
                 __IO uint32_t  MODEM_IE:1;
                 __IO uint32_t  RTO_IE:1;	  
                 __IO uint32_t  BUF_ERR_IE:1;
                 __IO uint32_t  WAKE_IE:1;
                 __IO uint32_t  ABAUD_IE:1;
	             __IO uint32_t  LIN_IE:1;
                 __I  uint32_t  RESERVE0:23;
                 } IER_BITS;
  };
  union {
  __IO uint32_t  ISR;
                 struct {
                 __IO uint32_t  RDA_IS:1;
                 __IO uint32_t  THRE_IS:1;
                 __IO uint32_t  RLS_IS:1;
                 __IO uint32_t  MODEM_IS:1;
                 __IO uint32_t  RTO_IS:1;
                 __IO uint32_t  BUF_ERR_IS:1;
                 __IO uint32_t  WAKE_IS:1;
                 __IO uint32_t  ABAUD_IS:1;
                 __IO uint32_t  LIN_IS:1;
                 __I  uint32_t  RESERVE0:23;
                 } ISR_BITS;
  };
  union {
  __IO uint32_t  TRSR;
                 struct {
                 __IO uint32_t  RS485_ADDET_F:1;
                 __IO uint32_t  ABAUD_F:1;
                 __IO uint32_t  ABAUD_TOUT_F:1;
                 __IO uint32_t  LIN_TX_F:1;
                 __IO uint32_t  LIN_RX_F:1;
                 __IO uint32_t  BUF_ERR_F:1;
                 __I  uint32_t  RESERVED0:2;
		         __IO uint32_t  SYNC_ERR_F:1;
		         __I  uint32_t  RESERVED1:23;
                 } TRSR_BITS;
  };
  union {
  __IO uint32_t  FSR;
                 struct {
                 __IO uint32_t  RX_OVER_F:1;
                 __IO uint32_t  RX_EMPTY_F:1;
                 __IO uint32_t  RX_FULL_F:1;
                 __I  uint32_t  RESERVE0:1;
                 __IO uint32_t  PE_F:1;
                 __IO uint32_t  FE_F:1;
                 __IO uint32_t  BI_F:1;
				 __I  uint32_t  RESERVE1:1;
                 __IO uint32_t  TX_OVER_F:1;
                 __IO uint32_t  TX_EMPTY_F:1;
                 __IO uint32_t  TX_FULL_F:1;
                 __IO uint32_t  TE_F:1;
                 __I  uint32_t  RESERVE2:4;
                 __IO uint32_t  RX_POINTER_F:4;
                 __I  uint32_t  RESERVE3:4;
                 __IO uint32_t  TX_POINTER_F:4; 
                 __I  uint32_t  RESERVE4:4;
                 } FSR_BITS;
  };
  union {
  __IO uint32_t  MCSR;
                 struct {
                 __IO uint32_t  LEV_RTS:1;
                 __IO uint32_t  RTS_ST:1;
                 __I  uint32_t  RESERVE0:14;               
                 __IO uint32_t  LEV_CTS:1;
                 __IO uint32_t  CTS_ST:1;
                 __IO uint32_t  DCT_F:1;
                 __I  uint32_t  RESERVED1:13;
                 } MCSR_BITS;
  };
  union {
  __IO uint32_t  TMCTL;
  				struct {
                 __IO uint32_t  TOIC:9;
                 __I  uint32_t  RESERVE0:7;
                 __IO uint32_t  DLY:8;
                 __I  uint32_t  RESERVE1:8;
                 } TMCTL_BITS;
  };
  union {
  __IO uint32_t  BAUD;
                 struct {
                 __IO uint32_t  BRD:16;
                 __I  uint32_t  RESERVE0:15;
                 __IO uint32_t  DIV_16_EN:1;
                 } BAUD_BITS;
  };
  uint32_t  RESERVED0[2];
  union {
  __IO uint32_t  IRCR;
                 struct {
                 __I  uint32_t  RESERVE0:1;				 	
                 __IO uint32_t  TX_SELECT:1;
                 __I  uint32_t  RESERVE1:3;				 
                 __IO uint32_t  INV_TX:1;            
                 __IO uint32_t  INV_RX:1;            
                 __I  uint32_t  RESERVE2:25;
                 } IRCR_BITS;
  };
  union {
  __IO uint32_t  ALT_CTL;
  				struct {
                 __IO uint32_t  LIN_TX_BCNT:3;
                 __I  uint32_t  RESERVE0:1;
                 __IO uint32_t  LIN_HEAD_SEL:2;
                 __IO uint32_t  LIN_RX_EN:1;            
                 __IO uint32_t  LIN_TX_EN:1;            
                 __IO uint32_t  BIT_ERR_EN:1;
                 __I  uint32_t  RESERVE1:7;
				 __IO uint32_t  RS485_NMM:1;
				 __IO uint32_t  RS485_AAD:1;
				 __IO uint32_t  RS485_AUD:1;
				 __IO uint32_t  RS485_ADD_EN:1;
                 __I  uint32_t  RESERVE2:4;				 
				 __IO uint32_t  ADDR_PID_MATCH:8;
                 } ALT_CTL_BITS;
  };
  union {
  __IO uint32_t  FUN_SEL;
                 struct {
                 __IO uint32_t  FUN_SEL:2;
	             __I  uint32_t  RESERVE0:30;
                 } FUN_SEL_BITS;   
  };
} UART_TypeDef;


/*
 * @brief Universal Serial Bus (USB)
 */
typedef struct
{
  union {
  __IO uint32_t  CTRL;
                 struct {
                 __IO uint32_t  USB_EN:1;
                 __IO uint32_t  PHY_EN:1;
                 __IO uint32_t  PWRDB:1;
                 __IO uint32_t  DPPU_EN:1;
                 __IO uint32_t  DRVSE0:1;
                 __I  uint32_t  RESERVE0:3;
                 __IO uint32_t  RWAKEUP:1;
                 __IO uint32_t  WAKEUP_EN:1;
                      uint32_t  RESERVED1:22;
                 } CTRL_BITS;
  };
  union {
  __I  uint32_t  BUSSTS;
                 struct {
                 __IO uint32_t  USBRST:1;
                 __IO uint32_t  SUSPEND:1;
                 __IO uint32_t  RESUME:1;
                 __IO uint32_t  TIMEOUT:1;
                 __IO uint32_t  FLDET:1;
                      uint32_t  RESERVED0:27;
                 } BUSSTS_BITS;
  };
  union {
  __IO uint32_t  INTEN;
                 struct {
                 __IO uint32_t  BUSEVT_IE:1;
                 __IO uint32_t  USBEVT_IE:1;
                 __IO uint32_t  FLDET_IE:1;
                 __IO uint32_t  WAKEUP_IE:1;
                      uint32_t  RESERVED0:28;
                 } INTEN_BITS;
  };
  union {
  __IO uint32_t  INTSTS;
                 struct {
                 __IO uint32_t  BUS:1;
                 __IO uint32_t  USB:1;
                 __IO uint32_t  FLD:1;
                 __IO uint32_t  WKEUP:1;
                      uint32_t  RESERVED0:12;
                 __IO uint32_t  EPTF:6;
                      uint32_t  RESERVED1:9;
                 __IO uint32_t  SETUP:1;
                 } INTSTS_BITS;
  };
  union {
  __IO uint32_t  DADDR;
                 struct {
                 __IO uint32_t  DADDR:7;
                      uint32_t  RESERVED0:25;
                 } DADDR_BITS;
  };
  union {
  __I  uint32_t  EPSTS;
                 struct {
                      uint32_t  RESERVED0:7;
                 __IO uint32_t  OVERRUN:1;
                 __IO uint32_t  STS0:4;
                 __IO uint32_t  STS1:4;
                 __IO uint32_t  STS2:4;
                 __IO uint32_t  STS3:4;
                 __IO uint32_t  STS4:4;
                 __IO uint32_t  STS5:4;
                 } EPSTS_BITS;
  };
  union {
  __IO uint32_t  BUFSEG;
                 struct {
                      uint32_t  RESERVED0:3;
                 __IO uint32_t  BUFSEG:6;
                      uint32_t  RESERVED1:23;
                 } BUFSEG_BITS;
  };
       uint32_t  RESERVED0;
  union {
  __IO uint32_t  BUFSEG0;
                 struct {
                      uint32_t  RESERVED0:3;
                 __IO uint32_t  BUFSEG:6;
                      uint32_t  RESERVED1:23;
                 } BUFSEG0_BITS;
  };
  union {
  __IO uint32_t  MXPLD0;
                 struct {
                 __IO uint32_t  MXPLD:9;
                      uint32_t  RESERVED0:23;
                 } MXPLD0_BITS;
  };
  union {
  __IO uint32_t  CFG0;
                 struct {
                 __IO uint32_t  EP_NUM:4;
                 __IO uint32_t  ISOCH:1;
                 __IO uint32_t  EPMODE:2;
                 __IO uint32_t  DSQ_SYNC:1;
                 __IO uint32_t  CSTALL:1;
                 __IO uint32_t  SSTALL:1;
                      uint32_t  RESERVED0:22;
                 } CFG0_BITS;
  };
       uint32_t  RESERVED1;
  union {
  __IO uint32_t  BUFSEG1;
                 struct {
                      uint32_t  RESERVED0:3;
                 __IO uint32_t  BUFSEG:6;
                      uint32_t  RESERVED1:23;
                 } BUFSEG1_BITS;
  };
  union {
  __IO uint32_t  MXPLD1;
                 struct {
                 __IO uint32_t  MXPLD:9;
                      uint32_t  RESERVED0:23;
                 } MXPL1_BITS;
  };
   union {
  __IO uint32_t  CFG1;
                 struct {
                 __IO uint32_t  EP_NUM:4;
                 __IO uint32_t  ISOCH:1;
                 __IO uint32_t  EPMODE:2;
                 __IO uint32_t  DSQ_SYNC:1;
                 __IO uint32_t  CSTALL:1;
                 __IO uint32_t  SSTALL:1;
                      uint32_t  RESERVED0:22;
                 } CFG1_BITS;
  };
       uint32_t  RESERVED2;
  union {
  __IO uint32_t  BUFSEG2;
                 struct {
                      uint32_t  RESERVED0:3;
                 __IO uint32_t  BUFSEG:6;
                      uint32_t  RESERVED1:23;
                 } BUFSEG2_BITS;
  };
  union {
  __IO uint32_t  MXPLD2;
                 struct {
                 __IO uint32_t  MXPLD:9;
                      uint32_t  RESERVED0:23;
                 } MXPLD2_BITS;
  };
  union {
  __IO uint32_t  CFG2;
                 struct {
                 __IO uint32_t  EP_NUM:4;
                 __IO uint32_t  ISOCH:1;
                 __IO uint32_t  EPMODE:2;
                 __IO uint32_t  DSQ_SYNC:1;
                 __IO uint32_t  CSTALL:1;
                 __IO uint32_t  SSTALL:1;
                      uint32_t  RESERVED0:22;
                 } CFG2_BITS;
  };
       uint32_t  RESERVED3;
  union {
  __IO uint32_t  BUFSEG3;
                 struct {
                      uint32_t  RESERVED0:3;
                 __IO uint32_t  BUFSEG:6;
                      uint32_t  RESERVED1:23;
                 } BUFSEG3_BITS;
  };
  union {
  __IO uint32_t  MXPLD3;
                 struct {
                 __IO uint32_t  MXPLD:9;
                      uint32_t  RESERVED0:23;
                 } MXPLD3_BITS;
  };
  union {
  __IO uint32_t  CFG3;
                 struct {
                 __IO uint32_t  EP_NUM:4;
                 __IO uint32_t  ISOCH:1;
                 __IO uint32_t  EPMODE:2;
                 __IO uint32_t  DSQ_SYNC:1;
                 __IO uint32_t  CSTALL:1;
                 __IO uint32_t  SSTALL:1;
                      uint32_t  RESERVED0:22;
                 } CFG3_BITS;
  };
       uint32_t  RESERVED4;
  union {
  __IO uint32_t  BUFSEG4;
                 struct {
                      uint32_t  RESERVED0:3;
                 __IO uint32_t  BUFSEG:6;
                      uint32_t  RESERVED1:23;
                 } BUFSEG4_BITS;
  };
  union {
  __IO uint32_t  MXPLD4;
                 struct {
                 __IO uint32_t  MXPLD:9;
                      uint32_t  RESERVED0:23;
                 } MXPLD4_BITS;
  };
  union {
  __IO uint32_t  CFG4;
                 struct {
                 __IO uint32_t  EP_NUM:4;
                 __IO uint32_t  ISOCH:1;
                 __IO uint32_t  EPMODE:2;
                 __IO uint32_t  DSQ_SYNC:1;
                 __IO uint32_t  CSTALL:1;
                 __IO uint32_t  SSTALL:1;
                      uint32_t  RESERVED0:22;
                 } CFG4_BITS;
  };
       uint32_t  RESERVED5;
  union {
  __IO uint32_t  BUFSEG5;
                 struct {
                      uint32_t  RESERVED0:3;
                 __IO uint32_t  BUFSEG:6;
                      uint32_t  RESERVED1:23;
                 } BUFSEG5_BITS;
  };
   union {
  __IO uint32_t  MXPLD5;
                 struct {
                 __IO uint32_t  MXPLD:9;
                      uint32_t  RESERVED0:23;
                 } MXPLD5_BITS;
  };
  union {
  __IO uint32_t  CFG5;
                 struct {
                 __IO uint32_t  EP_NUM:4;
                 __IO uint32_t  ISOCH:1;
                 __IO uint32_t  EPMODE:2;
                 __IO uint32_t  DSQ_SYNC:1;
                 __IO uint32_t  CSTALL:1;
                 __IO uint32_t  SSTALL:1;
                      uint32_t  RESERVED0:22;
                 } CFG5_BITS;
  };
       uint32_t  RESERVED6[10];
  union {
  __IO uint32_t  PDMA;
                 struct {
                 __IO uint32_t  PDMA_RW:1;
                 __IO uint32_t  PDMA_TRG:1;
                 __IO uint32_t  BYTEM:1;
                 __IO uint32_t  PDMA_RST:1;
                      uint32_t  RESERVED0:28;
                } PDMA_BITS;
  };
} USBD_TypeDef;


/*  
 * @brief Digital-to-Analog Converter (DAC)
 */
typedef struct
{
  union {
  __IO uint32_t  CTL0;
                 struct {
                      uint32_t  RESERVED0:1;
                 __IO uint32_t  EN:1;
                 __IO uint32_t  IE:1;
                      uint32_t  RESERVED1:1; 
                 __IO uint32_t  LSEL:3;
                 __IO uint32_t  RESERVED2:1; 
                 __IO uint32_t  PWONDACTMSEL:2;
                      uint32_t  RESERVED3:6;
                 __IO uint32_t  PWONDACTRANSCNT:8;
                 __IO uint32_t  DACPWONSTBCNT:8;
                 } CTL0_BITS;
  };
  union {
  __IO uint32_t  DATA0;
                 struct {
                 __IO uint32_t  DAT:12;
                      uint32_t  RESERVED0:20;
                 } DATA0_BITS;
  };
  union {
  __IO uint32_t  STS0;
                 struct {
                 __IO uint32_t  IFG:1;
                 __IO uint32_t  STFG:1;
                 __IO uint32_t  BUSY:1;
                      uint32_t  RESERVED1:29;
                 } STS0_BITS;
  };
  uint32_t  RESERVED0;
  union {
  __IO uint32_t  CTL1;
                 struct {
                      uint32_t  RESERVED0:1;
                 __IO uint32_t  EN:1;
                 __IO uint32_t  IE:1;
                      uint32_t  RESERVED1:1; 
                 __IO uint32_t  LSEL:3;
                 __IO uint32_t  RESERVED2:1; 
                 __IO uint32_t  PWONDACTMSEL:2;
                      uint32_t  RESERVED3:6;
                 __IO uint32_t  PWONDACTRANSCNT:8;
                 __IO uint32_t  DACPWONSTBCNT:8;
                 } CTL1_BITS;
  };
  union {
  __IO uint32_t  DATA1;
                 struct {
                 __IO uint32_t  DAT:12;
                      uint32_t  RESERVED0:20;
                 } DATA1_BITS;
  };
  union {
  __IO uint32_t  STS1;
                 struct {
                 __IO uint32_t  IFG:1;
                 __IO uint32_t  STFG:1;
                 __IO uint32_t  BUSY:1;
                      uint32_t  RESERVED1:29;
                 } STS1_BITS;
  };  
  uint32_t  RESERVED1;
  union {
  __IO uint32_t  COMCTL;
                 struct {
                 __IO uint32_t  WAITDACCONV:8;
                 __IO uint32_t  GRP:1;
				 __IO uint32_t  REFSEL:2;
                      uint32_t  RESERVED1:21;
                 } COMCTL_BITS;
  };   
} DAC_TypeDef;


/*  
 * @brief LCD Display Driver
 */
typedef struct
{
  union {
  __IO uint32_t  CTL;
                 struct {
                 __IO uint32_t  EN:1;
                 __IO uint32_t  MUX:2;
                 __IO uint32_t  FREQ:3;
                      uint32_t  RESERVED0:1;				 
                 __IO uint32_t  BLINK:1;
                 __IO uint32_t  PDDISP_EN:1;
                 __IO uint32_t  PDINT_EN:1;
                      uint32_t  RESERVED1:22;
                } CTL_BITS;
  };
  union {
  __IO uint32_t  DISPCTL;
                 struct {
                 __IO uint32_t  CPUMP_EN:1;
                 __IO uint32_t  BIAS_SEL:2;
                      uint32_t  RESERVED0:1;
                 __IO uint32_t  IBRL_EN:1;
                      uint32_t  RESERVED1:1;
                 __IO uint32_t  BV_SEL:1;
                      uint32_t  RESERVED2:1;
                 __IO uint32_t  CPUMP_VOL_SET:3;
                 __IO uint32_t  CPUMP_FREQ:3;
                      uint32_t  RESERVED3:18;
                 } DISPCTL_BITS;
  };
  __IO uint32_t  MEM_0;
  __IO uint32_t  MEM_1;
  __IO uint32_t  MEM_2;
  __IO uint32_t  MEM_3;
  __IO uint32_t  MEM_4;
  __IO uint32_t  MEM_5;
  __IO uint32_t  MEM_6;
  __IO uint32_t  MEM_7;
  union {
  __IO uint32_t  FCR;
                 struct {
                 __IO uint32_t  FCEN:1;
                 __IO uint32_t  INTEN:1;
                 __IO uint32_t  PRESCL:2;
                 __IO uint32_t  FCV:6;
                      uint32_t  RESERVED0:22;
                 } FCR_BITS;
  };
  union {
  __IO uint32_t  FCSTS;
                 struct {
                 __IO uint32_t  FCSTS:1;
                 __IO uint32_t  PDSTS:1;
                      uint32_t  RESERVED0:30;
                 } FCSTS_BITS;
  };
} LCD_TypeDef;


/*  
 * @brief Capacitive Touch-Key Sensing Engine
 */
typedef struct
{
  union {
  __IO uint32_t  CTL;
                 struct {
                 __IO uint32_t  MUX:4;
                 __IO uint32_t  FREQ:2;
                 __IO uint32_t  EXT_CAP_EN:1;
                 __IO uint32_t  RESERVED0:1;
                 __IO uint32_t  CUR_CTRL:4;
                 __IO uint32_t  START:1;
                 __IO uint32_t  SEN_SEL:2;
                 __IO uint32_t  EN:1;
                      uint32_t  RESERVED1:16;
                 } CTL_BITS;
  };
  union {
  __IO uint32_t  STAT;
                 struct {
                 __IO uint32_t  BUSY:1;
                 __IO uint32_t  DAT_RDY:1;
                 __IO uint32_t  SEN_FAIL:1;
                      uint32_t  RESERVED0:1;
                 __IO uint32_t  SEN_MATCH_LEVEL:4;
                      uint32_t  RESERVED1:24;
                 } STAT_BITS;
  };
  __IO uint32_t  DATA;
  union {
  __IO uint32_t  INTEN;
                 struct {
                 __IO uint32_t  RESERVED0:1;
                 __IO uint32_t  DAT_RDY_INT_EN:1;
                 __IO uint32_t  SEN_FAIL_INT_EN:1;
                      uint32_t  RESERVED1:29;
                 } INTEN_BITS;
  };
} TK_TypeDef;


/*  
 * @brief Analog-to-Digital Converters (ADC)
 */
typedef struct
{
  __I  uint32_t  RESULT0;
  __I  uint32_t  RESULT1;
  __I  uint32_t  RESULT2;
  __I  uint32_t  RESULT3;
  __I  uint32_t  RESULT4;
  __I  uint32_t  RESULT5;
  __I  uint32_t  RESULT6;
  __I  uint32_t  RESULT7;
  __I  uint32_t  RESULT8;
  __I  uint32_t  RESULT9;
  __I  uint32_t  RESULT10;

       uint32_t  RESERVED0[1];

  union {
  __IO uint32_t  CR;
                 struct {
                 __IO uint32_t  ADEN:1;
                 __IO uint32_t  ADIE:1;
                 __IO uint32_t  ADMD:2;
                 __IO uint32_t  TRGS:2;
                 __IO uint32_t  TRGCOND:2;
                 __IO uint32_t  TRGEN:1;
                 __IO uint32_t  PTEN:1;
                 __IO uint32_t  RESERVED0:1;
                 __IO uint32_t  ADST:1;
                 __IO uint32_t  TMSEL:2;
                 __IO uint32_t  RESERVED1:1;
				 __IO uint32_t  TMTRGMOD:1;
                 __IO uint32_t  REFSEL:2;
                      uint32_t  RESERVED2:14;
                 } CR_BITS;
  };
  union {
  __IO uint32_t  CHER;
                 struct {
                 __IO uint32_t  CHEN0:1;
                 __IO uint32_t  CHEN1:1;
                 __IO uint32_t  CHEN2:1;
                 __IO uint32_t  CHEN3:1;
                 __IO uint32_t  CHEN4:1;
                 __IO uint32_t  CHEN5:1;
                 __IO uint32_t  CHEN6:1;
                 __IO uint32_t  CHEN7:1;
                 __IO uint32_t  CHEN8:1;
                 __IO uint32_t  CHEN9:1;
                 __IO uint32_t  CHEN10:1;
                 __IO uint32_t  CH10SEL:2;
                      uint32_t  RESERVED0:19;
                 } CHER_BITS;
  };
  union {
  __IO uint32_t  CMPR0;
                 struct {
                 __IO uint32_t  CMPEN:1;
                 __IO uint32_t  CMPIE:1;
                 __IO uint32_t  CMPCOND:1;
                 __IO uint32_t  CMPCH:4;
                      uint32_t  RESERVED0:1;
                 __IO uint32_t  CMPMATCNT:4;
                      uint32_t  RESERVED1:4;
                 __IO uint32_t  CMPD:12;
                      uint32_t  RESERVED2:4;
                } CMPR0_BITS;
  };
  union {
  __IO uint32_t  CMPR1;
                 struct {
                 __IO uint32_t  CMPEN:1;
                 __IO uint32_t  CMPIE:1;
                 __IO uint32_t  CMPCOND:1;
                 __IO uint32_t  CMPCH:4;
                      uint32_t  RESERVED0:1;
                 __IO uint32_t  CMPMATCNT:4;
                      uint32_t  RESERVED1:4;
                 __IO uint32_t  CMPD:12;
                      uint32_t  RESERVED2:4;
                } CMPR1_BITS;
  };
  union {
  __IO uint32_t  SR;
                 struct {
                 __IO uint32_t  ADF:1;
                 __IO uint32_t  CMPF0:1;
                 __IO uint32_t  CMPF1:1;
                 __IO uint32_t  BUSY:1;
                 __IO uint32_t  CHANNEL:4;                      
                 __IO uint32_t  VALID:11;
				 	  uint32_t  RESERVED0:1;
                 __IO uint32_t  OVERRUN:11;
                      uint32_t  RESERVED1:1;
                 } SR_BITS;
  };
       uint32_t  RESERVED1[7];
  __I  uint32_t  PDMA;
  union {
  __IO uint32_t  DELSEL;
                 struct {
				 __IO uint32_t  EN2STDELAY:8;
				 __IO uint32_t  TMPDMACNT:8;
                 __IO uint32_t  STHOLDCNT:8;
					  uint32_t  RESERVED0:8;
				 }DELSEL_BITS;

  };
} ADC_TypeDef;


/* 
 * @brief Smart Card Controller (SC) 
 */
typedef struct
{
  union {
  __I  uint32_t  RBR;
  __O  uint32_t  THR;
  };
  union {
  __IO uint32_t  CTL;
                 struct {
                 __IO uint32_t  SC_CEN:1;
                 __IO uint32_t  DIS_RX:1;
                 __IO uint32_t  DIS_TX:1;
                 __IO uint32_t  AUTO_CON_EN:1;
                 __IO uint32_t  CON_SEL:2;
                 __IO uint32_t  RX_FTRI_LEV:2;
                 __IO uint32_t  BGT:5;
                 __IO uint32_t  TMR_SEL:2;
                 __IO uint32_t  SLEN:1;
                 __IO uint32_t  RX_ERETRY:3;
                 __IO uint32_t  RX_ERETRY_EN:1;
                 __IO uint32_t  TX_ERETRY:3;
                 __IO uint32_t  TX_ERETRY_EN:1;
                 __IO uint32_t  CD_DEB_SEL:2;
                      uint32_t  RESERVED1:6;
                 } CTL_BITS;
  };
  union {
  __IO uint32_t  ALTCTL;
                 struct {
                 __IO uint32_t  TX_RST:1;
                 __IO uint32_t  RX_RST:1;
                 __IO uint32_t  DACT_EN:1;
                 __IO uint32_t  ACT_EN:1;
                 __IO uint32_t  WARST_EN:1;
                 __IO uint32_t  TMR0_SEN:1;
                 __IO uint32_t  TMR1_SEN:1;
                 __IO uint32_t  TMR2_SEN:1;
                 __IO uint32_t  INIT_SEL:2;
                      uint32_t  RESERVED0:2;
                 __IO uint32_t  RX_BGT_EN:1;   
                 __IO uint32_t  TMR0_ATV:1;
                 __IO uint32_t  TMR1_ATV:1;
                 __IO uint32_t  TMR2_ATV:1;
                      uint32_t  RESERVED1:16;
                 } ALTCTL_BITS;
  };
  __IO uint32_t  EGTR;
  __IO uint32_t  RFTMR;
  union {
  __IO uint32_t  ETUCR;
                 struct {
                 __IO uint32_t  ETU_RDIV:12;
                      uint32_t	RESERVED0:3;
                 __IO uint32_t  COMPEN_EN:1;
                      uint32_t  RESERVED1:16;
                 } ETUCR_BITS;
  };
  union {
  __IO uint32_t  IER;
                 struct {
                 __IO uint32_t  RDA_IE:1;
                 __IO uint32_t  TBE_IE:1;
                 __IO uint32_t  TERR_IE:1;
                 __IO uint32_t  TMR0_IE:1;
                 __IO uint32_t  TMR1_IE:1;
                 __IO uint32_t  TMR2_IE:1;
                 __IO uint32_t  BGT_IE:1;
                 __IO uint32_t  CD_IE:1;
                 __IO uint32_t  INIT_IE:1;
                 __IO uint32_t  RTMR_IE:1;
                 __IO uint32_t  ACON_ERR_IE:1;
                      uint32_t  RESERVED0:21;
                 } IER_BITS;
  };
  union {
  __IO uint32_t  ISR;
                 struct {
                 __IO uint32_t  RDA_IS:1;
                 __IO uint32_t  TBE_IS:1;
                 __IO uint32_t  TERR_IS:1;
                 __IO uint32_t  TMR0_IS:1;
                 __IO uint32_t  TMR1_IS:1;
                 __IO uint32_t  TMR2_IS:1;
                 __IO uint32_t  BGT_IS:1;
                 __IO uint32_t  CD_IS:1;
                 __IO uint32_t  INIT_IS:1;
                 __IO uint32_t  RTMR_IS:1;
                 __IO uint32_t  ACON_ERR_IS:1;
                      uint32_t  RESERVED0:21;
                 } ISR_BITS;
  };
  union {
  __IO uint32_t  TRSR;
                 struct {
                 __IO uint32_t  RX_OVER_F:1;
                 __IO uint32_t  RX_EMPTY_F:1;
                 __IO uint32_t  RX_FULL_F:1;
                      uint32_t  RESERVED0:1;
                 __IO uint32_t  RX_EPA_F:1;
                 __IO uint32_t  RX_EFR_F:1;
                 __IO uint32_t  RX_EBR_F:1;
                      uint32_t  RESERVED1:1;
                 __IO uint32_t  TX_OVER_F:1;
                 __IO uint32_t  TX_EMPTY_F:1;
                 __IO uint32_t  TX_FULL_F:1;
                      uint32_t  RESERVED2:5;                 
                 __IO uint32_t  RX_POINT_F:3;
                      uint32_t  RESERVED3:2;
                 __IO uint32_t  RX_REERR:1;
                 __IO uint32_t  RX_OVER_REERR:1;
                 __IO uint32_t  RX_ATV:1;
                 __IO uint32_t  TX_POINT_F:3;
                      uint32_t  RESERVED4:2;
                 __IO uint32_t  TX_REERR:1;
                 __IO uint32_t  TX_OVER_REERR:1;
                 __IO uint32_t  TX_ATV:1;
                 } TRSR_BITS;
  };
  union {
  __IO uint32_t  PINCSR;
                 struct {
                 __IO uint32_t  POW_EN:1;
                 __IO uint32_t  SC_RST:1;
                 __IO uint32_t  CD_REM_F:1;
                 __IO uint32_t  CD_INS_F:1;
                 __IO uint32_t  CD_PIN_ST:1;
                 __IO uint32_t  CLK_STOP_LEV:1;
                 __IO uint32_t  CLK_KEEP:1;
                 __IO uint32_t  ADAC_CD_EN:1;
                 __I  uint32_t  SC_OEN_ST:1;
                 __IO uint32_t  SC_DATA_O:1;
                 __IO uint32_t  CD_LEV:1;
                      uint32_t  RESERVED0:5;
                 __IO uint32_t  SC_DATA_I_ST:1;
                      uint32_t  RESERVED1:14;
                 __IO uint32_t  LOOPBACK:1;
                 } PINCSR_BITS;
  };
  union {
  __IO uint32_t  TMR0;
                 struct {
                 __IO uint32_t  CNT:24;
                 __IO uint32_t  MODE:4;
                      uint32_t  RESERVED0:4;
                 } TMR0_BITS;
  };
  union {
  __IO uint32_t  TMR1;
                 struct {
                 __IO uint32_t  CNT:8;
                      uint32_t  RESERVED0:16;				 
                 __IO uint32_t  MODE:4;
                      uint32_t  RESERVED1:4;
                 } TMR1_BITS;
  };
  union {
  __IO uint32_t  TMR2;
                 struct {
                 __IO uint32_t  CNT:8;
                      uint32_t  RESERVED0:16;				 
                 __IO uint32_t  MODE:4;
                      uint32_t  RESERVED1:4;
                 } TMR2_BITS;
  };
} SC_TypeDef;


/* 
 * @brief I2S
 */
typedef struct
{
  union {
  __IO uint32_t  CTRL;
                 struct {
                 __IO uint32_t  I2SEN:1;
                 __IO uint32_t  TXEN:1;
                 __IO uint32_t  RXEN:1;
                 __IO uint32_t  MUTE:1;
                 __IO uint32_t  WORDWIDTH:2;
                 __IO uint32_t  MONO:1;
                 __IO uint32_t  FORMAT:1;
                 __IO uint32_t  SLAVE:1;
                 __IO uint32_t  TXTH:3;
	             __IO uint32_t  RXTH:3;
	             __IO uint32_t  MCLKEN:1;
                 __IO uint32_t  RCHZCEN:1;
                 __IO uint32_t  LCHZCEN:1;
                 __IO uint32_t  CLR_TXFIFO:1;
                 __IO uint32_t  CLR_RXFIFO:1;
	             __IO uint32_t  TXDMA:1;
	             __IO uint32_t  RXDMA:1;	
	                  uint32_t  RESERVED0:10;
                 } CTRL_BITS;
  };
  union {
  __IO uint32_t  CLKDIV;
                 struct {
                 __IO uint32_t  MCLK_DIV:3;
                      uint32_t  RESERVED0:5;
	             __IO uint32_t  BCLK_DIV:8;
                      uint32_t  RESERVED1:16;
                 } CLKDIV_BITS;
  };
  union {
  __IO uint32_t  INTEN;
                 struct {
                 __IO uint32_t  RXUDFIE:1;
	             __IO uint32_t  RXOVFIE:1;
	             __IO uint32_t  RXTHIE:1;
                      uint32_t  RESERVED0:5;
	             __IO uint32_t  TXUDFIE:1;
	             __IO uint32_t  TXOVFIE:1;
	             __IO uint32_t  TXTHIE:1;
	             __IO uint32_t  RZCIE:1;
	             __IO uint32_t  LZCIE:1;
                      uint32_t  RESERVED1:19;
                 } INTIE_BITS;
  };
  union {
  __IO uint32_t  STATUS;
                 struct {
                 __I  uint32_t  I2SINT:1;
	             __I  uint32_t  I2SRXINT:1;
	             __I  uint32_t  I2STXINT:1;
	             __I  uint32_t  RIGHT:1;
                      uint32_t  RESERVED0:4;
	             __IO uint32_t  RXUDF:1;
	             __IO uint32_t  RXOVF:1;
	             __I  uint32_t  RXTHF:1;
	             __I  uint32_t  RXFULL:1;
	             __I  uint32_t  RXEMPTY:1;
	                  uint32_t  RESERVED1:3;
	             __IO uint32_t  TXUDF:1;
	             __IO uint32_t  TXOVF:1;
	             __I  uint32_t  TXTHF:1;
	             __I  uint32_t  TXFULL:1;
	             __I  uint32_t  TXEMPTY:1;
	             __I  uint32_t  TXBUSY:1;
	             __IO uint32_t  RZCF:1;
	             __IO uint32_t  LZCF:1;	
	             __I  uint32_t  RX_LEVEL:4;
	             __I  uint32_t  TX_LEVEL:4;
                 } STATUS_BITS;
  };
  __O uint32_t  TXFIFO;
  __I uint32_t  RXFIFO;
} I2S_TypeDef;


/*  
 * @brief System Management Control Registers (GCR)
 */
typedef struct
{
  __I  uint32_t  PDID;
  union {
  __IO uint32_t  RST_SRC;
                 struct {
                 __IO uint32_t  POR:1;
	             __IO uint32_t  PAD:1;
	             __IO uint32_t  WDT:1;
				      uint32_t  RESERVED0:1;
	             __IO uint32_t  BOD:1;
	             __IO uint32_t  SYS:1;
	                  uint32_t  RESERVED1:1;
	             __IO uint32_t  CPU:1;    
	                  uint32_t  RESERVED2:24;
                 } RST_SRC_BITS;
  };
  union {
  __IO uint32_t  IPRST_CTL1;
                 struct {
                 __IO uint32_t  CHIP_RST:1;
                 __IO uint32_t  CPU_RST:1;
                 __IO uint32_t  PDMA_RST:1;
                 __IO uint32_t  EBI_RST:1;
                 __I  uint32_t  RESERVED0:28;
                 } IPRST_CTL1_BITS;
  };
  union {
  __IO uint32_t  IPRST_CTL2;
                 struct {
                      uint32_t  RESERVED0:1;
                 __IO uint32_t  GPIO_RST:1;
                 __IO uint32_t  TMR0_RST:1;
                 __IO uint32_t  TMR1_RST:1;
                 __IO uint32_t  TMR2_RST:1;
                 __IO uint32_t  TMR3_RST:1;
                      uint32_t  RESERVED1:2;
                 __IO uint32_t  I2C0_RST:1;
                 __IO uint32_t  I2C1_RST:1;
                      uint32_t  RESERVED2:2;
                 __IO uint32_t  SPI0_RST:1;
                 __IO uint32_t  SPI1_RST:1;
                 __IO uint32_t  SPI2_RST:1;
                      uint32_t  RESERVED3:1;
                 __IO uint32_t  UART0_RST:1;
                 __IO uint32_t  UART1_RST:1;
                      uint32_t  RESERVED4:2;
                 __IO uint32_t  PWM0_RST:1;
                 __IO uint32_t  PWM1_RST:1;
                      uint32_t  RESERVED5:2;
                 __IO uint32_t  TK_RST:1;
                 __IO uint32_t  DAC_RST:1;
                 __IO uint32_t  LCD_RST:1;
                 __IO uint32_t  USBD_RST:1;
                 __IO uint32_t  ADC_RST:1;
                 __IO uint32_t  I2S_RST:1;
                 __IO uint32_t  SC0_RST:1;
                 __IO uint32_t  SC1_RST:1;
                 } IPRST_CTL2_BITS;
  };
  __IO uint32_t  CPR;
  uint32_t  RESERVED0[7];
  union {
  __IO uint32_t  PA_L_MFP;
                 struct {
                 __IO uint32_t  PA0:3;
	                  uint32_t  RESERVED0:1;
                 __IO uint32_t  PA1:3;
	                  uint32_t  RESERVED1:1;
                 __IO uint32_t  PA2:3;
	                  uint32_t  RESERVED2:1;
                 __IO uint32_t  PA3:3;
	                  uint32_t  RESERVED3:1;
                 __IO uint32_t  PA4:3;
	                  uint32_t  RESERVED4:1;
                 __IO uint32_t  PA5:3;
	                  uint32_t  RESERVED5:1;
                 __IO uint32_t  PA6:3;
	                  uint32_t  RESERVED6:1;
                 __IO uint32_t  PA7:3;
	                  uint32_t  RESERVED7:1;
                 } PA_L_MFP_BITS;
  };
  union {
  __IO uint32_t  PA_H_MFP;
                 struct {
                 __IO uint32_t  PA8:3;
	                  uint32_t  RESERVED0:1;
                 __IO uint32_t  PA9:3;
	                  uint32_t  RESERVED1:1;
                 __IO uint32_t  PA10:3;
	                  uint32_t  RESERVED2:1;
                 __IO uint32_t  PA11:3;
	                  uint32_t  RESERVED3:1;
                 __IO uint32_t  PA12:3;
	                  uint32_t  RESERVED4:1;
                 __IO uint32_t  PA13:3;
	                  uint32_t  RESERVED5:1;
                 __IO uint32_t  PA14:3;
	                  uint32_t  RESERVED6:1;
                 __IO uint32_t  PA15:3;
	                  uint32_t  RESERVED7:1;
                 } PA_H_MFP_BITS;
  };
  union {
  __IO uint32_t  PB_L_MFP;
                 struct {
                 __IO uint32_t  PB0:3;
	                  uint32_t  RESERVED0:1;
                 __IO uint32_t  PB1:3;
	                  uint32_t  RESERVED1:1;
                 __IO uint32_t  PB2:3;
	                  uint32_t  RESERVED2:1;
                 __IO uint32_t  PB3:3;
	                  uint32_t  RESERVED3:1;
                 __IO uint32_t  PB4:3;
	                  uint32_t  RESERVED4:1;
                 __IO uint32_t  PB5:3;
	                  uint32_t  RESERVED5:1;
                 __IO uint32_t  PB6:3;
	                  uint32_t  RESERVED6:1;
                 __IO uint32_t  PB7:3;
	                  uint32_t  RESERVED7:1;
                 } PB_L_MFP_BITS;
  };
  union {
  __IO uint32_t  PB_H_MFP;
                 struct {
                 __IO uint32_t  PB8:3;
	                  uint32_t  RESERVED0:1;
                 __IO uint32_t  PB9:3;
	                  uint32_t  RESERVED1:1;
                 __IO uint32_t  PB10:3;
	                  uint32_t  RESERVED2:1;
                 __IO uint32_t  PB11:3;
	                  uint32_t  RESERVED3:1;
                 __IO uint32_t  PB12:3;
	                  uint32_t  RESERVED4:1;
                 __IO uint32_t  PB13:3;
	                  uint32_t  RESERVED5:1;
                 __IO uint32_t  PB14:3;
	                  uint32_t  RESERVED6:1;
                 __IO uint32_t  PB15:3;
	                  uint32_t  RESERVED7:1;
                 } PB_H_MFP_BITS;
  };
  union {
  __IO uint32_t  PC_L_MFP;
                 struct {
                 __IO uint32_t  PC0:3;
	                  uint32_t  RESERVED0:1;
                 __IO uint32_t  PC1:3;
	                  uint32_t  RESERVED1:1;
                 __IO uint32_t  PC2:3;
	                  uint32_t  RESERVED2:1;
                 __IO uint32_t  PC3:3;
	                  uint32_t  RESERVED3:1;
                 __IO uint32_t  PC4:3;
	                  uint32_t  RESERVED4:1;
                 __IO uint32_t  PC5:3;
	                  uint32_t  RESERVED5:1;
                 __IO uint32_t  PC6:3;
	                  uint32_t  RESERVED6:1;
                 __IO uint32_t  PC7:3;
	                  uint32_t  RESERVED7:1;
                 } PC_L_MFP_BITS;
  };
  union {
  __IO uint32_t  PC_H_MFP;
                 struct {
                 __IO uint32_t  PC8:3;
	                  uint32_t  RESERVED0:1;
                 __IO uint32_t  PC9:3;
	                  uint32_t  RESERVED1:1;
                 __IO uint32_t  PC10:3;
	                  uint32_t  RESERVED2:1;
                 __IO uint32_t  PC11:3;
	                  uint32_t  RESERVED3:1;
                 __IO uint32_t  PC12:3;
	                  uint32_t  RESERVED4:1;
                 __IO uint32_t  PC13:3;
	                  uint32_t  RESERVED5:1;
                 __IO uint32_t  PC14:3;
	                  uint32_t  RESERVED6:1;
                 __IO uint32_t  PC15:3;
	                  uint32_t  RESERVED7:1;
                 } PC_H_MFP_BITS;
  };
  union {
  __IO uint32_t  PD_L_MFP;
                 struct {
                 __IO uint32_t  PD0:3;
	                  uint32_t  RESERVED0:1;
                 __IO uint32_t  PD1:3;
	                  uint32_t  RESERVED1:1;
                 __IO uint32_t  PD2:3;
	                  uint32_t  RESERVED2:1;
                 __IO uint32_t  PD3:3;
	                  uint32_t  RESERVED3:1;
                 __IO uint32_t  PD4:3;
	                  uint32_t  RESERVED4:1;
                 __IO uint32_t  PD5:3;
	                  uint32_t  RESERVED5:1;
                 __IO uint32_t  PD6:3;
	                  uint32_t  RESERVED6:1;
                 __IO uint32_t  PD7:3;
	                  uint32_t  RESERVED7:1;
                 } PD_L_MFP_BITS;
  };
  union {
  __IO uint32_t  PD_H_MFP;
                 struct {
                 __IO uint32_t  PD8:3;
	                  uint32_t  RESERVED0:1;
                 __IO uint32_t  PD9:3;
	                  uint32_t  RESERVED1:1;
                 __IO uint32_t  PD10:3;
	                  uint32_t  RESERVED2:1;
                 __IO uint32_t  PD11:3;
	                  uint32_t  RESERVED3:1;
                 __IO uint32_t  PD12:3;
	                  uint32_t  RESERVED4:1;
                 __IO uint32_t  PD13:3;
	                  uint32_t  RESERVED5:1;
                 __IO uint32_t  PD14:3;
	                  uint32_t  RESERVED6:1;
                 __IO uint32_t  PD15:3;
	                  uint32_t  RESERVED7:1;
                 } PD_H_MFP_BITS;
  };
  union {
  __IO uint32_t  PE_L_MFP;
                 struct {
                 __IO uint32_t  PE0:3;
	                  uint32_t  RESERVED0:1;
                 __IO uint32_t  PE1:3;
	                  uint32_t  RESERVED1:1;
                 __IO uint32_t  PE2:3;
	                  uint32_t  RESERVED2:1;
                 __IO uint32_t  PE3:3;
	                  uint32_t  RESERVED3:1;
                 __IO uint32_t  PE4:3;
	                  uint32_t  RESERVED4:1;
                 __IO uint32_t  PE5:3;
	                  uint32_t  RESERVED5:1;
                 __IO uint32_t  PE6:3;
	                  uint32_t  RESERVED6:1;
                 __IO uint32_t  PE7:3;
	                  uint32_t  RESERVED7:1;
                 } PE_L_MFP_BITS;
  };
  union {
  __IO uint32_t  PE_H_MFP;
                 struct {
                 __IO uint32_t  PE8:3;
	                  uint32_t  RESERVED0:1;
                 __IO uint32_t  PE9:3;
	                  uint32_t  RESERVED1:1;
                 __IO uint32_t  PE10:3;
	                  uint32_t  RESERVED2:1;
                 __IO uint32_t  PE11:3;
	                  uint32_t  RESERVED3:1;
                 __IO uint32_t  PE12:3;
	                  uint32_t  RESERVED4:1;
                 __IO uint32_t  PE13:3;
	                  uint32_t  RESERVED5:1;
                 __IO uint32_t  PE14:3;
	                  uint32_t  RESERVED6:1;
                 __IO uint32_t  PE15:3;
	                  uint32_t  RESERVED7:1;
                 } PE_H_MFP_BITS;
  };
  union {
  __IO uint32_t  PF_L_MFP;
                 struct {
                 __IO uint32_t  PF0:3;
	                  uint32_t  RESERVED0:1;
                 __IO uint32_t  PF1:3;
	                  uint32_t  RESERVED1:1;
                 __IO uint32_t  PF2:3;
	                  uint32_t  RESERVED2:1;
                 __IO uint32_t  PF3:3;
	                  uint32_t  RESERVED3:1;
                 __IO uint32_t  PF4:3;
	                  uint32_t  RESERVED4:1;
                 __IO uint32_t  PF5:3;
	                  uint32_t  RESERVED5:1;
	                  uint32_t  RESERVED6:8;
                 } PF_L_MFP_BITS;
  };
       uint32_t  RESERVED3[1];
  __IO uint32_t  PORCTL;
  union {
  __IO uint32_t  BODCTL;
                 struct {
                 __IO uint32_t  BOD17_EN:1;
                 __IO uint32_t  BOD20_EN:1;
                 __IO uint32_t  BOD25_EN:1;
	                  uint32_t  RESERVED0:1;
                 __IO uint32_t  BOD17_RST:1;
                 __IO uint32_t  BOD20_RST:1;
                 __IO uint32_t  BOD25_RST:1;
	                  uint32_t  RESERVED1:1;
                 __IO uint32_t  BOD17_INT:1;
                 __IO uint32_t  BOD20_INT:1;
                 __IO uint32_t  BOD25_INT:1;
	                  uint32_t  RESERVED2:1;
	                  uint32_t  RESERVED3:20;
                 } BODCTL_BITS;
  };
  union {
  __IO uint32_t  BODSTS;
                 struct {
		              uint32_t  RESERVED0:1;
                 __IO uint32_t  BOD17_OUT:1;
                 __IO uint32_t  BOD20_OUT:1;
                 __IO uint32_t  BOD25_OUT:1;				 
	                  uint32_t  RESERVED1:28;
                 } BODSTS_BITS;
  };
  union {
  __IO uint32_t  VREFCTL;
                 struct {
                 __IO uint32_t  BGP_EN:1;
                 __IO uint32_t  REG_EN:1;
                 __IO uint32_t  SEL25:1;
					  uint32_t  RESERVED0:5;
				 __IO uint32_t  BGP_TRIM:4;
	                  uint32_t  RESERVED1:20;
                 } VREFCTL_BITS;
  };
  union {
  __IO uint32_t  LDOCTL;
                 struct {
                 __IO uint32_t  ADD_3UA:1;
                 __IO uint32_t  ADD_15UA:1;
                 __IO uint32_t  LDO_LEVEL:2;
	                  uint32_t  RESERVED0:28;
                 } LDOCTL_BITS;
  };
       uint32_t  RESERVED4[3];
  union {
  __IO uint32_t  IRCTRIMCTL;
                 struct {
                 __IO uint32_t  TRIM_SEL:2;
	                  uint32_t  RESERVED0:2;
                 __IO uint32_t  TRIM_LOOP:2;
	                  uint32_t  RESERVED1:26;
                 } IRCTRIMCTL_BITS;
  };
  union {
  __IO uint32_t  IRCTRIMIER;
                 struct {
	                  uint32_t  RESERVED0:1;
                 __IO uint32_t  TRIM_FAIL_IE:1;
                 __IO uint32_t  ERR_32K_IE:1;
	                  uint32_t  RESERVED1:29;
                 } IRCTRIMIER_BITS;
  };
  union {
  __IO uint32_t  IRCTRIMISR;
                 struct {
	                  uint32_t  FREQ_LOCK:1;
                 __IO uint32_t  TRIM_FAIL_IS:1;
                 __IO uint32_t  ERR_32K_IS:1;
	                  uint32_t  RESERVED0:29;
                 } IRCTRIMISR_BITS;
  };
       uint32_t  RESERVED5[29];
  __IO uint32_t  RegLockAddr;
} GCR_TypeDef;


/*  
 * @brief Clock Control Registers (CLK)
 */
typedef struct
{
  union {
  __IO uint32_t  PWRCTL; 
                 struct {
                 __IO uint32_t  HXT_EN:1;
                 __IO uint32_t  LXT_EN:1;
                 __IO uint32_t  HIRC_EN:1;
                 __IO uint32_t  LIRC_EN:1;
                 __IO uint32_t  WK_DLY:1;
                 __IO uint32_t  PD_WK_IE:1;
                 __IO uint32_t  PD_EN:1;
                      uint32_t  RESERVED0:1;
                 __IO uint32_t  HXT_SELXT:1;
                 __IO uint32_t  HXT_GAIN:1;
                 __IO uint32_t  LXT_SCNT:1;
                      uint32_t  RESERVED1:21;
                 } PWRCTL_BITS;
  };
  union {
  __IO uint32_t  AHBCLK;
                 struct {
                 __IO uint32_t  GPIO_EN:1;
                 __IO uint32_t  PDMA_EN:1;
                 __IO uint32_t  ISP_EN:1;
                 __IO uint32_t  EBI_EN:1;
                 __IO uint32_t  SRAM_EN:1;
                 __IO uint32_t  TICK_EN:1;
                      uint32_t  RESERVED0:26;
                 } AHBCLK_BITS;
  };
  union {
  __IO uint32_t  APBCLK;
                 struct {
                 __IO uint32_t  WDT_EN:1;
                 __IO uint32_t  RTC_EN:1;
                 __IO uint32_t  TMR0_EN:1;
                 __IO uint32_t  TMR1_EN:1;
                 __IO uint32_t  TMR2_EN:1;
                 __IO uint32_t  TMR3_EN:1;
                 __IO uint32_t  FDIV_EN:1;
                      uint32_t  RESERVED0:1;
                 __IO uint32_t  I2C0_EN:1;
                 __IO uint32_t  I2C1_EN:1;
                      uint32_t  RESERVED1:2;
                 __IO uint32_t  SPI0_EN:1;
                 __IO uint32_t  SPI1_EN:1;
                 __IO uint32_t  SPI2_EN:1;
                      uint32_t  RESERVED2:1;
                 __IO uint32_t  UART0_EN:1;
                 __IO uint32_t  UART1_EN:1;
	                  uint32_t  RESERVED3:2;
                 __IO uint32_t  PWM0_CH01_EN:1;
                 __IO uint32_t  PWM0_CH23_EN:1;
	             __IO uint32_t  PWM1_CH01_EN:1;
                 __IO uint32_t  PWM1_CH23_EN:1;
                 __IO uint32_t  TK_EN:1;
                 __IO uint32_t  DAC_EN:1;
                 __IO uint32_t  LCD_EN:1;
                 __IO uint32_t  USBD_EN:1;
                 __IO uint32_t  ADC_EN:1;
                 __IO uint32_t  I2S_EN:1;
                 __IO uint32_t  SC0_EN:1;
                 __IO uint32_t  SC1_EN:1;

                 } APBCLK_BITS;
  };
  union {
  __IO uint32_t  CLKSTATUS;
                 struct {
                 __IO uint32_t  HXT_STB:1;
                 __IO uint32_t  LXT_STB:1;
                 __IO uint32_t  PLL_STB:1;
                 __IO uint32_t  LIRC_STB:1;
                 __IO uint32_t  HIRC_STB:1;
                      uint32_t  RESERVED0:2;
                 __IO uint32_t  CLK_SW_FAIL:1;
                      uint32_t  RESERVED1:24;
                 } CLKSTATUS_BITS;
  };
  __IO uint32_t  CLKSEL0;
  union {
  __IO uint32_t  CLKSEL1;
                 struct {
                 __IO uint32_t  UART_S:2;
                 __IO uint32_t  ADC_S:2;
                 __IO uint32_t  PWM0_CH01_S:2;
                 __IO uint32_t  PWM0_CH23_S:2;
                 __IO uint32_t  TMR0_S:3;
                      uint32_t  RESERVED0:1;
                 __IO uint32_t  TMR1_S:3;
                      uint32_t  RESERVED1:1;
                 __IO uint32_t  TK_S:2;
                 __IO uint32_t  LCD_S:1;
                      uint32_t  RESERVED2:13;
                 } CLKSEL1_BITS;
  };
 
union {
__IO uint32_t  CLKSEL2;
                 struct {
                      uint32_t  RESERVED0:2;      
                 __IO uint32_t  FRQDIV_S:2;
                 __IO uint32_t  PWM1_CH01_S:2;
                 __IO uint32_t  PWM1_CH23_S:2;
                 __IO uint32_t  TMR2_S:3;
                      uint32_t  RESERVED1:1;
                 __IO uint32_t  TMR3_S:3;
                      uint32_t  RESERVED2:1;       
                 __IO uint32_t  I2S_S:2;
                 __IO uint32_t  SC_S:2;
                      uint32_t  RESERVED3:12;
                 } CLKSEL2_BITS;
  };
  union {
  __IO uint32_t  CLKDIV0;
                  struct {
                 __IO uint32_t  HCLK_N:4;
                 __IO uint32_t  USB_N:4;
                 __IO uint32_t  UART_N:4;
                 __IO uint32_t  I2S_N:4;
                 __IO uint32_t  ADC_N:8;
                 __IO uint32_t  TK_N:4;
                 __IO uint32_t  SC0_N:4;
                 } CLKDIV0_BITS;
  };
    union {
  __IO uint32_t  CLKDIV1;
                  struct {
                 __IO uint32_t  SC1_N:4;
                      uint32_t  RESERVED0:28;
                 } CLKDIV1_BITS;
  };
  union {
  __IO uint32_t  PLLCTL;
                 struct {
                 __IO uint32_t  FB_DV:6;
                      uint32_t  RESERVED0:2;
                 __IO uint32_t  IN_DV:2;
                      uint32_t  RESERVED1:2;
                 __IO uint32_t  OUT_DV:1;
                      uint32_t  RESERVED2:3;
                 __IO uint32_t  PD:1;
                 __IO uint32_t  PLL_SRC:1;
                      uint32_t  RESERVED3:14;
                 } PLLCTL_BITS;
  };
  union {
  __IO uint32_t  FRQDIV;
                 struct {    
                 __IO uint32_t  FSEL:4;
	             __IO uint32_t  FDIV_EN:1;
                 __I  uint32_t  RESERVE:27;
                 } FRQDIV_BITS;
  };
  __IO uint32_t  TESTCLK;
  __IO uint32_t  WK_INTSTS;
} CLK_TypeDef;


/*  
 * @brief Interrupt Source Identify Registers
 */
typedef struct
{
  __I  uint32_t  IRQ0_SRC;
  __I  uint32_t  IRQ1_SRC;
  __I  uint32_t  IRQ2_SRC;
  __I  uint32_t  IRQ3_SRC;
  __I  uint32_t  IRQ4_SRC;
  __I  uint32_t  IRQ5_SRC;
  __I  uint32_t  IRQ6_SRC;
  __I  uint32_t  IRQ7_SRC;
  __I  uint32_t  IRQ8_SRC;
  __I  uint32_t  IRQ9_SRC;
  __I  uint32_t  IRQ10_SRC;
  __I  uint32_t  IRQ11_SRC;
  __I  uint32_t  IRQ12_SRC;
  __I  uint32_t  IRQ13_SRC;
  __I  uint32_t  IRQ14_SRC;
  __I  uint32_t  IRQ15_SRC;
  __I  uint32_t  IRQ16_SRC;
  __I  uint32_t  IRQ17_SRC;
  __I  uint32_t  IRQ18_SRC;
  __I  uint32_t  IRQ19_SRC;
  __I  uint32_t  IRQ20_SRC;  
  __I  uint32_t  IRQ21_SRC;
  __I  uint32_t  IRQ22_SRC;
  __I  uint32_t  IRQ23_SRC;
  __I  uint32_t  IRQ24_SRC;
  __I  uint32_t  IRQ25_SRC;
  __I  uint32_t  IRQ26_SRC;
  __I  uint32_t  IRQ27_SRC;
  __I  uint32_t  IRQ28_SRC;
  __I  uint32_t  IRQ29_SRC;
  __I  uint32_t  IRQ30_SRC;
  __I  uint32_t  IRQ31_SRC;
  __IO uint32_t  NMI_SEL;
  __IO uint32_t  MCU_IRQ;
} INTID_TypeDef;


/*  
 * @brief General Purpose I/O pins (GPIO)
 */
typedef struct
{
  union {
  __IO uint32_t  PMD;
                 struct {
                 __IO uint32_t PMD0:2;
                 __IO uint32_t PMD1:2;
                 __IO uint32_t PMD2:2;
                 __IO uint32_t PMD3:2;
                 __IO uint32_t PMD4:2;
                 __IO uint32_t PMD5:2;
                 __IO uint32_t PMD6:2;
                 __IO uint32_t PMD7:2;
                 __IO uint32_t PMD8:2;
                 __IO uint32_t PMD9:2;
                 __IO uint32_t PMD10:2;
                 __IO uint32_t PMD11:2;
                 __IO uint32_t PMD12:2;
                 __IO uint32_t PMD13:2;
                 __IO uint32_t PMD14:2;
                 __IO uint32_t PMD15:2;
                 } PMD_BITS;
  };
  __IO uint32_t  OFFD;
  __IO uint32_t  DOUT;
  __IO uint32_t  DMASK;
  __I  uint32_t  PIN;
  __IO uint32_t  DBEN;
  __IO uint32_t  IMD;
  union {
  __IO uint32_t  IER;
                 struct {
                 __IO uint32_t  FIER:16;
                 __IO uint32_t  RIER:16;
                 } IER_BITS;
  };
  __IO uint32_t  ISR;
  __IO uint32_t  PUEN;
} GPIO_TypeDef;


/*  
 * @brief GPIO De-bounce Cycle Control
 */
typedef struct
{
  union {
  __IO uint32_t  CON;
                 struct {
                 __IO uint32_t  DBCLKSEL:4;
                 __IO uint32_t  DBCLKSRC:1;
                 __IO uint32_t  DBCLKEN:1;
                 __I  uint32_t  RESERVE:26;    
                 } CON_BITS;
  };
} GPIODBNCE_TypeDef;


/*  
 * @brief General Purpose I/O bit mode (GPIO bit mode)
 */
typedef struct
{
  __IO uint32_t  GP_BIT0;
  __IO uint32_t  GP_BIT1;
  __IO uint32_t  GP_BIT2;
  __IO uint32_t  GP_BIT3;
  __IO uint32_t  GP_BIT4;
  __IO uint32_t  GP_BIT5;
  __IO uint32_t  GP_BIT6;
  __IO uint32_t  GP_BIT7;
  __IO uint32_t  GP_BIT8;
  __IO uint32_t  GP_BIT9;
  __IO uint32_t  GP_BIT10;
  __IO uint32_t  GP_BIT11;
  __IO uint32_t  GP_BIT12;
  __IO uint32_t  GP_BIT13;
  __IO uint32_t  GP_BIT14;
  __IO uint32_t  GP_BIT15;
} GPIOBIT_TypeDef;


/*  
 * @brief direct memory access (VDMA)
 */
typedef struct
{
  union {
  __IO uint32_t  CSR;
                 struct {
                 __IO uint32_t  VDMACEN:1;
                 __IO uint32_t  SW_RST:1;
                      uint32_t  RESERVED0:8;
                 __IO uint32_t  STRIDE_EN:1;
                 __IO uint32_t  DIR_SEL:1;
                      uint32_t  RESERVED1:11;
                 __IO uint32_t  TRIG_EN:1;
                      uint32_t  RESERVED2:8;
                 } CSR_BITS;
  };
  __IO uint32_t  SAR;
  __IO uint32_t  DAR;
  __IO uint32_t  BCR;
       uint32_t  RESERVED0;
  __I  uint32_t  CSAR;
  __I  uint32_t  CDAR;
  union {
  __I  uint32_t  CBCR;
                 struct {
                 __IO uint32_t  CBCR:16;
                      uint32_t  RESERVED0:16;
                 } CBCR_BITS;
  };
  union {
  __IO uint32_t  IER;
                 struct {
                 __IO uint32_t  TABORT:1;
                 __IO uint32_t  BLKD:1;
                      uint32_t  RESERVED0:30;
                 } IER_BITS;
  };
  union {
  __IO uint32_t  ISR;
                 struct {
                 __IO uint32_t  TABORT:1;
                 __IO uint32_t  BLKD:1;
                      uint32_t  RESERVED0:30;
                 } ISR_BITS;
  };
       uint32_t  RESERVED1;
  union {
  __IO uint32_t  SASOCR;
                 struct {
                 __IO uint32_t  SASTOBL:16;
                 __IO uint32_t  STBC:16;
                 } SASOCR_BITS;
  };
  union {
  __IO uint32_t  DASOCR;
                 struct {
                 __IO uint32_t  DASTOBL:16;
                 __IO uint32_t  RESERVED0:16;
                 } DASOCR_BITS;
  };
       uint32_t  RESERVED2[19];
  __I  uint32_t  BUF0;
  __I  uint32_t  BUF1;
} VDMA_TypeDef;


/*  
 * @brief Peripheral direct memory access (PDMA)
 */
typedef struct
{
  union {
  __IO uint32_t  CSR;
                 struct {
                 __IO uint32_t  PDMACEN:1;
                 __IO uint32_t  SW_RST:1;
                 __IO uint32_t  MODE_SEL:2;
                 __IO uint32_t  SAD_SEL:2;
                 __IO uint32_t  DAD_SEL:2;
                      uint32_t  RESERVED0:4;
                 __IO uint32_t  TO_EN:1;
                      uint32_t  RESERVED1:6;
                 __IO uint32_t  APB_TWS:2;
                      uint32_t  RESERVED2:2;
                 __IO uint32_t  TRIG_EN:1;
                      uint32_t  RESERVED3:8;
                 } CSR_BITS;
  };
  __IO uint32_t  SAR;
  __IO uint32_t  DAR;
  __IO uint32_t  BCR;
       uint32_t  RESERVED0;
  __I  uint32_t  CSAR;
  __I  uint32_t  CDAR;
  union {
  __I  uint32_t  CBCR;
                 struct {
                 __IO uint32_t  CBCR:24;
                      uint32_t  RESERVED0:8;
                 } CBCR_BITS;
  };
  union {
  __IO uint32_t  IER;
                 struct {
                 __IO uint32_t  TABORT:1;
                 __IO uint32_t  BLKD:1;
                 __IO uint32_t  WAR_TC:1;
                      uint32_t  RESERVED0:1;
                 __IO uint32_t  WAR_HT:1;
                 __IO uint32_t  TO_IE:1;
                      uint32_t  RESERVED1:26;
                 } IER_BITS;
  };
  union {
  __IO uint32_t  ISR;
                 struct {
                 __IO uint32_t  TABORT:1;
                 __IO uint32_t  BLKD:1;
	             __IO uint32_t  WAR_TC:1;
                      uint32_t  RESERVED0:1;
	             __IO uint32_t  WAR_HT:1;
                      uint32_t  RESERVED1:1;
	             __IO uint32_t  TO_IS:1;
                      uint32_t  RESERVED2:25;
                 } ISR_BITS;
  };
  union {
  __IO uint32_t  TCR;
                 struct {
                 __IO uint32_t  TCR:16;
                      uint32_t  RESERVED:16;
                 } TCR_BITS;
  };
       uint32_t  RESERVED1[21];
  __I  uint32_t  BUF0;
} PDMA_TypeDef;


/*  
 * @brief PDMA Global Control Registers
 */
typedef struct
{
  union {
  __IO uint32_t  CSR;
                 struct {
                      uint32_t  RESERVED0:8;
                 __IO uint32_t  HCLK0_EN:1;
                 __IO uint32_t  HCLK1_EN:1;
                 __IO uint32_t  HCLK2_EN:1;
                 __IO uint32_t  HCLK3_EN:1;
                 __IO uint32_t  HCLK4_EN:1;
                      uint32_t  RESERVED1:19;
                 } CSR_BITS;
  };
  union {
  __IO uint32_t  PDSSR0;
                 struct {
                      uint32_t  RESERVED0:8;
                 __IO uint32_t  CH1_SEL:5;
                      uint32_t  RESERVED1:3;
                 __IO uint32_t  CH2_SEL:5;
                      uint32_t  RESERVED2:3;
                 __IO uint32_t  CH3_SEL:5;
                      uint32_t  RESERVED3:3;
                 } PDSSR0_BITS;
  };
  union {
  __IO uint32_t  PDSSR1;
                 struct {
                 __IO uint32_t  CH4_SEL:5;
                      uint32_t  RESERVED0:27;
                 } PDSSR1_BITS;
  };
  __IO uint32_t  ISR;
} PDMAGCR_TypeDef;


/*  
 * @brief Flash Memory Controller (FMC)
 */
typedef struct
{
  union {
  __IO uint32_t  ISPCON;
                 struct {
                 __IO uint32_t  ISPEN:1;
                 __IO uint32_t  BS:1;
	                  uint32_t  RESERVED0:2;
                 __IO uint32_t  CFGUEN:1;
	             __IO uint32_t  LDUEN:1;
                 __IO uint32_t  ISPFF:1;
                 __IO uint32_t  SWRST:1;
                 __IO uint32_t  PT:3;
	                  uint32_t  RESERVED1:1;
	             __IO uint32_t  ET:3;
                      uint32_t  RESERVED2:17;
                 } ISPCON_BITS;
  };
  __IO uint32_t  ISPADR;
  __IO uint32_t  ISPDAT;
  union {
  __IO uint32_t  ISPCMD;
                 struct {
                 __IO uint32_t  FCTRL:4;
                 __IO uint32_t  FCEN:1;
                 __IO uint32_t  FOEN:1;
                      uint32_t  RESERVED0:26;
                 } ISPCMD_BITS;
  };
  union {
  __IO uint32_t  ISPTRG;
                 struct {
                 __IO uint32_t  ISPGO:1;
                      uint32_t  RESERVED0:31;
                 } ISPTRG_BITS;
  };
  __I  uint32_t  DFBADR;
  union {
  __IO uint32_t  FATCON;
                 struct {
                      uint32_t  RESERVED0:4;
                 __IO uint32_t  LFOM:1;
                 __IO uint32_t  FIDLE:1;
                 __IO uint32_t  MFOM:1;
                 __IO uint32_t  FBOFF:1;
                      uint32_t  RESERVED1:24;
                 } FATCON_BITS;
  };

  __I  uint32_t   RESERVED0[9];
  union {
  __IO uint32_t  ISPSTA;
                 struct {
                 __I  uint32_t  ISPBUSY:1;
                 __I  uint32_t  CBS:2;
                      uint32_t  RESERVED0:3;
                 __IO uint32_t  ISPFF:1;
                      uint32_t  RESERVED1:2;
                 __IO uint32_t  VECMAP:12;
                      uint32_t  RESERVED2:11;
                 } ISPSTA_BITS;
  };
} FMC_TypeDef;


/*  
 * @brief External Bus Interface (EBI)
 */
typedef struct
{
  union {
  __IO uint32_t  EBICON;
                 struct {
                 __IO uint32_t  ExtEN:1;
                 __IO uint32_t  ExtBW16:1;
	                  uint32_t  RESERVED0:6;
                 __IO uint32_t  MCLKDIV:3;
	             __IO uint32_t  RESERVED1:5;
                 __IO uint32_t  ExttALE:3;
                      uint32_t  RESERVED2:13;
                 } EBICON_BITS;
  };
  union {
  __IO uint32_t  EXTIME;
                 struct {
                 __IO uint32_t  ExttACC:5;
                 __IO uint32_t  RESERVED0:3;
                 __IO uint32_t  ExttAHD:3;
	                  uint32_t  RESERVED1:1;
                 __IO uint32_t  ExtIW2X:4;
	             __IO uint32_t  ExtLR2W:4;
	                  uint32_t  RESERVED2:4;
                 __IO uint32_t  ExtIR2R:4;
                      uint32_t  RESERVED3:4;
                 } EXTIME_BITS;
  };
} EBI_TypeDef;


/*
 * @}
 */

#if defined ( __CC_ARM   )
#pragma no_anon_unions
#endif

/*
 * @addtogroup Peripheral_memory_map
 * @{
 */
 
/*!<Peripheral and SRAM base address */
#define SRAM_BASE             ((uint32_t)0x20000000)
#define APB1PERIPH_BASE       ((uint32_t)0x40000000)
#define APB2PERIPH_BASE       ((uint32_t)0x40100000)
#define AHBPERIPH_BASE        ((uint32_t)0x50000000)

/*!<Peripheral memory map */
#define WDT_BASE	          (APB1PERIPH_BASE + 0x04000)
#define RTC_BASE	          (APB1PERIPH_BASE + 0x08000)
#define TIMER0_BASE	          (APB1PERIPH_BASE + 0x10000)
#define TIMER1_BASE	          (APB1PERIPH_BASE + 0x10100)
#define I2C0_BASE	          (APB1PERIPH_BASE + 0x20000)
#define SPI0_BASE	          (APB1PERIPH_BASE + 0x30000)
#define PWM0_BASE	          (APB1PERIPH_BASE + 0x40000)
#define UART0_BASE	          (APB1PERIPH_BASE + 0x50000)
#define USBD_BASE	          (APB1PERIPH_BASE + 0x60000)
#define USBD_SRAM_BASE	      (APB1PERIPH_BASE + 0x60100)
#define DAC_BASE	          (APB1PERIPH_BASE + 0xA0000)
#define LCD_BASE	          (APB1PERIPH_BASE + 0xB0000)
#define TK_BASE	              (APB1PERIPH_BASE + 0xC0000)
#define SPI2_BASE             (APB1PERIPH_BASE + 0xD0000)
#define ADC_BASE	          (APB1PERIPH_BASE + 0xE0000)

#define TIMER2_BASE	          (APB2PERIPH_BASE + 0x10000)
#define TIMER3_BASE	          (APB2PERIPH_BASE + 0x10100)
#define SHADOW_BASE	   (APB1PERIPH_BASE + 0x10200)
#define I2C1_BASE	          (APB2PERIPH_BASE + 0x20000)
#define SPI1_BASE	          (APB2PERIPH_BASE + 0x30000)
#define PWM1_BASE	          (APB2PERIPH_BASE + 0x40000)
#define UART1_BASE	          (APB2PERIPH_BASE + 0x50000)
#define SC0_BASE	            (APB2PERIPH_BASE + 0x90000)
#define I2S_BASE	                 (APB2PERIPH_BASE + 0xA0000)
#define SC1_BASE	              (APB2PERIPH_BASE + 0xB0000)

#define GCR_BASE	          (AHBPERIPH_BASE + 0x00000)
#define CLK_BASE	          (AHBPERIPH_BASE + 0x00200)
#define INTID_BASE	          (AHBPERIPH_BASE + 0x00300)
#define GPIOA_BASE	          (AHBPERIPH_BASE + 0x04000)
#define GPIOB_BASE	          (AHBPERIPH_BASE + 0x04040)
#define GPIOC_BASE	          (AHBPERIPH_BASE + 0x04080)
#define GPIOD_BASE	          (AHBPERIPH_BASE + 0x040C0)
#define GPIOE_BASE	          (AHBPERIPH_BASE + 0x04100)
#define GPIOF_BASE	          (AHBPERIPH_BASE + 0x04140)
#define GPIODBNCE_BASE	    (AHBPERIPH_BASE + 0x04180)
#define GPIOBITA_BASE	      (AHBPERIPH_BASE + 0x04200)
#define GPIOBITB_BASE	      (AHBPERIPH_BASE + 0x04240)
#define GPIOBITC_BASE	      (AHBPERIPH_BASE + 0x04280)
#define GPIOBITD_BASE	      (AHBPERIPH_BASE + 0x042C0)
#define GPIOBITE_BASE	      (AHBPERIPH_BASE + 0x04300)
#define GPIOBITF_BASE	      (AHBPERIPH_BASE + 0x04340)
#define VDMA_BASE	          (AHBPERIPH_BASE + 0x08000)
#define PDMA1_BASE	          (AHBPERIPH_BASE + 0x08100)
#define PDMA2_BASE	          (AHBPERIPH_BASE + 0x08200)
#define PDMA3_BASE	          (AHBPERIPH_BASE + 0x08300)
#define PDMA4_BASE	          (AHBPERIPH_BASE + 0x08400)
#define PDMAGCR_BASE	    (AHBPERIPH_BASE + 0x08F00)
#define FMC_BASE	          (AHBPERIPH_BASE + 0x0C000)
#define EBI_BASE	          	   (AHBPERIPH_BASE + 0x10000)

/*
 * @}
 */

/* @addtogroup Peripheral_declaration
 * @{
 */  
#define WDT                   ((WDT_TypeDef *) WDT_BASE)
#define RTC                   ((RTC_TypeDef *) RTC_BASE)
#define TIMER0                ((TIMER_TypeDef *) TIMER0_BASE)
#define TIMER1   	          ((TIMER_TypeDef *) TIMER1_BASE)
#define TIMER2                ((TIMER_TypeDef *) TIMER2_BASE)
#define TIMER3   	          ((TIMER_TypeDef *) TIMER3_BASE)
#define SHADOW                ((SHADOW_TypeDef *) SHADOW_BASE)
#define I2C0                  ((I2C_TypeDef *) I2C0_BASE)
#define I2C1                  ((I2C_TypeDef *) I2C1_BASE)
#define SPI0                  ((SPI_TypeDef *) SPI0_BASE)
#define SPI1                  ((SPI_TypeDef *) SPI1_BASE)
#define SPI2                  ((SPI_TypeDef *) SPI2_BASE)
#define PWM0                  ((PWM_TypeDef *) PWM0_BASE)
#define PWM1                  ((PWM_TypeDef *) PWM1_BASE)
#define UART0                 ((UART_TypeDef *) UART0_BASE)
#define UART1                 ((UART_TypeDef *) UART1_BASE)
#define USBD                  ((USBD_TypeDef *) USBD_BASE)
#define DAC                   ((DAC_TypeDef *) DAC_BASE)
#define LCD                   ((LCD_TypeDef *) LCD_BASE)
#define TK                    ((TK_TypeDef *) TK_BASE)
#define ADC                   ((ADC_TypeDef *) ADC_BASE)
#define SC0                    ((SC_TypeDef *) SC0_BASE)
#define I2S                   ((I2S_TypeDef *) I2S_BASE)
#define SC1                    ((SC_TypeDef *) SC1_BASE)



#define GCR                   ((GCR_TypeDef *) GCR_BASE)
#define CLK                   ((CLK_TypeDef *) CLK_BASE)
#define INTID                 ((INTID_TypeDef *) INTID_BASE)
#define GPIOA                 ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB                 ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC                 ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD                 ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE                 ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF                 ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIODBNCE             ((GPIODBNCE_TypeDef *) GPIODBNCE_BASE)
#define GPIOBITA              ((GPIOBIT_TypeDef *) GPIOBITA_BASE)
#define GPIOBITB              ((GPIOBIT_TypeDef *) GPIOBITB_BASE)
#define GPIOBITC              ((GPIOBIT_TypeDef *) GPIOBITC_BASE)
#define GPIOBITD              ((GPIOBIT_TypeDef *) GPIOBITD_BASE)
#define GPIOBITE              ((GPIOBIT_TypeDef *) GPIOBITE_BASE)
#define GPIOBITF              ((GPIOBIT_TypeDef *) GPIOBITF_BASE)
#define VDMA                  ((VDMA_TypeDef *) VDMA_BASE)
#define PDMA1                 ((PDMA_TypeDef *) PDMA1_BASE)
#define PDMA2                 ((PDMA_TypeDef *) PDMA2_BASE)
#define PDMA3                 ((PDMA_TypeDef *) PDMA3_BASE)
#define PDMA4                 ((PDMA_TypeDef *) PDMA4_BASE)
#define PDMAGCR               ((PDMAGCR_TypeDef *) PDMAGCR_BASE)
#define FMC                   ((FMC_TypeDef *) FMC_BASE)
#define EBI                   ((EBI_TypeDef *) EBI_BASE)
/*
 * @}
 */

#define UNLOCKREG(x)        *((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x59;*((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x16;*((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x88
#define LOCKREG(x)          *((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x00;     


/*
 * @I/O routines and constant definitions
 * @{
 */
typedef volatile unsigned char  vu8;
typedef volatile unsigned long  vu32;
typedef volatile unsigned short vu16;
#define M8(adr)  (*((vu8  *) (adr)))
#define M16(adr) (*((vu16 *) (adr)))
#define M32(adr) (*((vu32 *) (adr)))

#define outpw(port,value)	*((volatile unsigned int *)(port))=value
#define inpw(port)			(*((volatile unsigned int *)(port)))
#define outpb(port,value)	*((volatile unsigned char *)(port))=value
#define inpb(port)			(*((volatile unsigned char *)(port)))
#define outps(port,value)	*((volatile unsigned short *)(port))=value
#define inps(port)			(*((volatile unsigned short *)(port)))

#define outp32(port,value)	*((volatile unsigned int *)(port))=value
#define inp32(port)			(*((volatile unsigned int *)(port)))
#define outp8(port,value)	*((volatile unsigned char *)(port))=value
#define inp8(port)			(*((volatile unsigned char *)(port)))
#define outp16(port,value)	*((volatile unsigned short *)(port))=value
#define inp16(port)			(*((volatile unsigned short *)(port)))


#ifndef E_SUCCESS
#define E_SUCCESS 	(0)
#endif
#ifndef NULL
#define NULL        (0)
#endif

#define TRUE	   	(1)
#define FALSE   	(0)

#define ENABLE     (1)
#define DISABLE    (0)

/* Define one bit mask */
#define BIT0	(0x00000001)
#define BIT1	(0x00000002)
#define BIT2	(0x00000004)
#define BIT3	(0x00000008)
#define BIT4	(0x00000010)
#define BIT5	(0x00000020)
#define BIT6	(0x00000040)
#define BIT7	(0x00000080)
#define BIT8	(0x00000100)
#define BIT9	(0x00000200)
#define BIT10	(0x00000400)
#define BIT11	(0x00000800)
#define BIT12	(0x00001000)
#define BIT13	(0x00002000)
#define BIT14	(0x00004000)
#define BIT15	(0x00008000)
#define BIT16	(0x00010000)
#define BIT17	(0x00020000)
#define BIT18	(0x00040000)
#define BIT19	(0x00080000)
#define BIT20	(0x00100000)
#define BIT21	(0x00200000)
#define BIT22	(0x00400000)
#define BIT23	(0x00800000)
#define BIT24	(0x01000000)
#define BIT25	(0x02000000)
#define BIT26	(0x04000000)
#define BIT27	(0x08000000)
#define BIT28	(0x10000000)
#define BIT29	(0x20000000)
#define BIT30	(0x40000000)
#define BIT31	(0x80000000)

/*
 * @}
 */

#define assert_param(expr) ((void)0)

#ifdef __cplusplus
}
#endif

#endif  // __NANO1xx_H__
